ST STM32F101xx - SPI_I 2 S Prescaler Register (SPI_I2 SPR)

Serial peripheral interface (SPI) RM0008
724/1096 Doc ID 13902 Rev 12
25.5.9 SPI_I
2
S prescaler register (SPI_I2SPR)
Address offset: 0x20
Reset value: 0000 0010 (0x0002)
Bit 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I
2
S is disabled.
Not used in SPI mode
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in.
Note: For correct operation, this bit should be configured when the I
2
S is disabled.
Not used in SPI mode
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MCKOE ODD I2SDIV
rw rw rw
Bits 15:10 Reserved: Forced to 0 by hardware
Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in master
mode.
Not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 25.4.3 on page 705
Note: This bit should be configured when the I
2
S is disabled. It is used only when the I
2
S is in master
mode.
Not used in SPI mode
Bit 7:0 I2SDIV: I2S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 25.4.3 on page 705
Note: These bits should be configured when the I
2
S is disabled. It is used only when the I
2
S is in
master mode.
Not used in SPI mode.