RM0008 Inter-integrated circuit (I
2
C) interface
Doc ID 13902 Rev 12 731/1096
Slave receiver
Following the address reception and after clearing ADDR, the slave receives bytes from the
SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
● An acknowledge pulse if the ACK bit is set
● The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bit is set.
If RxNE is set and the data in the DR register is not read before the end of the next data
reception, the BTF bit is set and the interface waits until BTF is cleared by a read from
I2C_SR1 followed by a read from the I2C_DR register, stretching SCL low (see Figure 271
Transfer sequencing).
Figure 271. Transfer sequence diagram for slave receiver
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets,
● The STOPF bit and generates an interrupt if the ITEVFEN bit is set.
Then the interface waits for a read of the SR1 register followed by a write to the CR1 register
(see Figure 271 Transfer sequencing EV4).
26.3.3 I
2
C master mode
In Master mode, the I
2
C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a Start condition and ends with a Stop condition.
Master mode is selected as soon as the Start condition is generated on the bus with a
START bit.
7-bit slave receiver
10-bit slave receiver
Legend: S= Start, S
r
= Repeated Start, P= Stop, A= Acknowledge,
EVx= Event (with interrupt if ITEVFEN=1)
EV1: ADDR=1, cleared by reading SR1 followed by reading SR2
EV2: RxNE=1 cleared by reading DR register.
EV4: STOPF=1, cleared by reading SR1 register followed by writing to the CR1 register
S Address AData1AData2A
.....
DataNA
P
EV1 EV2 EV2 EV2 EV4
S Header A Address AData1A
.....
DataNA P
EV1 EV2 EV2
EV4
ai15884b
Notes: 1- The EV1 event stretches SCL low until the end of the corresponding software sequence.
2- The EV2 software sequence must complete before the end of the current byte transfer.
To Next Page
Loading...
Need help?
General
