To Next Page

To Previous Page

RM0008 Ethernet (ETH): media access control (MAC) with DMA controller

Doc ID 13902 Rev 12 1011/1096

Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)

Address offset: 0x0028

Reset value: 0x0000 0000

This is the address through which the remote wakeup frame filter registers are written/read

by the application. The Wakeup frame filter register is actually a pointer to eight (not

transparent) such wakeup frame filter registers. Eight sequential write operations to this

address with the offset (0x0028) will write all wakeup frame filter registers. Eight sequential

read operations from this address with the offset (0x0028) will read all wakeup frame filter

registers. This register contains the higher 16 bits of the 7

MAC address. Refer to Remote

wakeup frame filter register section for additional information.

Figure 358. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)

Filter 0 Byte Mask

Filter 1 Byte Mask

Filter 2 Byte Mask

Filter 3 Byte Mask

RSVD

Filter 3

Command

RSVD

Filter 2

Command

RSVD

Filter 1

Command

RSVD

Filter 0

Command

Filter 3 Offset Filter 2 Offset Filter 1 Offset Filter 0 Offset

Filter 1 CRC - 16 Filter 0 CRC - 16

Filter 3 CRC - 16 Filter 2 CRC - 16

Wakeup frame filter reg0

Wakeup frame filter reg1

Wakeup frame filter reg2

Wakeup frame filter reg3

Wakeup frame filter reg4

Wakeup frame filter reg5

Wakeup frame filter reg6

Wakeup frame filter reg7

ai15648

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English

ST STM32F101xx User Manual

Table of Contents

Questions and Answers:

ST STM32F101xx Specifications

Related product manuals