ST STM32F101xx User Manual

Ethernet (ETH): media access control (MAC) with DMA controller RM0008
1012/1096 Doc ID 13902 Rev 12
Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
Address offset: 0x002C
Reset value: 0x0000 0000
The ETH_MACPMTCSR programs the request wakeup events and monitors the wakeup
events.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WFFRPR
Reserved
GU
Reserved
WFR
MPR
Reserved
WFE
MPE
PD
rs Res. rw rc_r rc_r rw rw rs
Bit 31 WFFRPR: Wakeup frame filter register pointer reset
When set, it resets the Remote wakeup frame filter register pointer to 0b000. It is automatically
cleared after 1 clock cycle.
Bits 30:10 Reserved
Bit 9 GU: Global unicast
When set, it enables any unicast packet filtered by the MAC (DAF) address recognition to be a
wakeup frame.
Bits 8:7 Reserved
Bit 6 WFR: Wakeup frame received
When set, this bit indicates the power management event was generated due to reception of a
wakeup frame. This bit is cleared by a read into this register.
Bit 5 MPR: Magic packet received
When set, this bit indicates the power management event was generated by the reception of a
Magic Packet. This bit is cleared by a read into this register.
Bits 4:3 Reserved
Bit 2 WFE: Wakeup frame enable
When set, this bit enables the generation of a power management event due to wakeup frame
reception.
Bit 1 MPE: Magic Packet enable
When set, this bit enables the generation of a power management event due to Magic Packet
reception.
Bit 0 PD: Power down
When this bit is set, all received frames will be dropped. This bit is cleared automatically when
a magic packet or wakeup frame is received, and Power-down mode is disabled. Frames
received after this bit is cleared are forwarded to the application. This bit must only be set
when either the Magic Packet Enable or Wakeup Frame Enable bit is set high.

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English