ST STM32F101xx User Manual

Digital-to-analog converter (DAC) RM0008
260/1096 Doc ID 13902 Rev 12
12.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000
12.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
DACC2DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:28 Reserved.
Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 15:12 Reserved.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR[11:0]
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR[11:0]
Reserved
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 19:16 Reserved.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel1.
Bits 3:0 Reserved.

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English