Analog-to-digital converter (ADC) RM0008
218/1096 Doc ID 13902 Rev 12
11.9 Dual ADC mode
In devices with two ADCs or more, dual ADC mode can be used (see Figure 29).
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0]
bits in the ADC1_CR1 register.
Note: In dual mode, when configuring conversion to be triggered by an external event, the user
must set the trigger for the master only and set a software trigger for the slave to prevent
spurious triggers to start unwanted slave conversion. However, external triggers must be
enabled on both master and slave ADCs.
The following six possible modes are implemented:
– Injected simultaneous mode
– Regular simultaneous mode
– Fast interleaved mode
– Slow interleaved mode
– Alternate trigger mode
– Independent mode
It is also possible to use the previous modes combined in the following ways:
– Injected simultaneous mode + Regular simultaneous mode
– Regular simultaneous mode + Alternate trigger mode
– Injected simultaneous mode + Interleaved mode
Note: In dual ADC mode, to read the slave converted data on the master data register, the DMA
bit must be enabled even if it is not used to transfer converted regular channel data.
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