RM0008 Serial peripheral interface (SPI)
Doc ID 13902 Rev 12 697/1096
25.4 I
2
S functional description
The I
2
S audio protocol is not available in low- and medium-density devices. This section
concerns only high-density, XL-density and connectivity line devices.
25.4.1 I
2
S general description
The block diagram of the I
2
S is shown in Figure 248.
Figure 248. I
2
S block diagram
The SPI could function as an audio I
2
S interface when the I
2
S capability is enabled (by
setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same
pins, flags and interrupts as the SPI.
Tx buffer
Shift register
16-bit
Communication
Rx buffer
16-bit
MOSI/ SD
Master control logic
MISO
SPI
baud rate generator
CK
I2SMOD
LSB first
LSB
First
SPE BR2 BR1 BR0
MSTR CPOL CPHA
Bidi
mode
Bidi
OE
CRC
EN
CRC
Next
DFF
Rx
only
SSM
SSI
Address and data bus
control
NSS/WS
BSY OVR MODF
CRC
ERR
CH
SIDE
TxE RxNE
I
2
S clock generator
MCK
I2S_CK
I2S
MOD
I2SE
CH
DATLEN
LEN
CKPOL
I2SCFG I2SSTD
MCKOE ODD I2SDIV[7:0]
[1:0] [1:0] [1:0]
UDR
I2SxCLK
ai14748
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