ST STM32F101xx User Manual

RM0008 Debug support (DBG)
Doc ID 13902 Rev 12 1069/1096
For the I
2
C, the user can choose to block the SMBUS timeout during a breakpoint.
31.16.3 Debug MCU configuration register
This register allows the configuration of the MCU under DEBUG. This concerns:
● Low-power mode support
● Timer and watchdog counter support
● bxCAN communication support
● Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res.
DBG_
TIM11_
STOP
DBG_
TIM10_
STOP
DBG_
TIM9_
STOP
DBG_
TIM14_
STOP
DBG_
TIM13_
STOP
DBG_
TIM12_
STOP
Reserved
DGB_C
AN2_ST
OP
DBG_
TIM7_
STOP
DBG_
TIM6_
STOP
DBG_
TIM5_
STOP
DBG_
TIM8_
STOP
DBG_I2C2
_SMBUS_
TIMEOUT
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_I2C1
_SMBUS_
TIMEOUT
DBG_
CAN1_
STOP
DBG_
TIM4_
STOP
DBG_
TIM3_
STOP
DBG_
TIM2_
STOP
DBG_
TIM1_
STOP
DBG_
WWDG_
STOP
DBG_
IWDG
STOP
TRACE_
MODE
[1:0]
TRACE_
IOEN
Reserved
DBG_
STAND
BY
DBG_
STOP
DBG_
SLEEP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 31 Reserved, must be kept cleared.
Bits 30:25 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=9..14)
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the outputs
are disabled (as if there were an emergency stop in response to a break event).
Bits 24:22 Reserved, must be kept cleared.
Bit 21 DBG_CAN2_STOP: Debug CAN2 stopped when core is halted
0: Same behavior as in normal mode
1: CAN2 receive registers are frozen
Bits 20:17 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=8..5)
0: The clock of the involved timer counter is fed even if the core is halted, and the outputs
behave normally.
1: The clock of the involved timer counter is stopped when the core is halted, and the outputs
are disabled (as if there were an emergency stop in response to a break event).

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English