ST STM32F101xx User Manual

Real-time clock (RTC) RM0008
468/1096 Doc ID 13902 Rev 12
18.3.5 RTC flag assertion
The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update
of the RTC Counter.
The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the
counter reaches 0x0000.
The RTC_Alarm and RTC Alarm flag (ALRF) (see Figure 180) are asserted on the last RTC
Core clock cycle before the counter reaches the RTC Alarm value stored in the Alarm
register increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC
Second flag must be synchronized by using one of the following sequences:
● Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm
and/or RTC Counter registers are updated.
● Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or
the RTC Counter register.
Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004
Figure 181. RTC Overflow waveform example with PR=0003
RTC_CNT 0000
0001
RTC_PR
0002 0001 0000 0003 0002 0001 0000 0003
0002
RTC_ALARM
0002 0001 0000 0003
0003
0002 0001 0000 0003
0004
0002 0001 0000 0003
ALRF
can be cleared by software
RTC_Second
RTCCLK
0005
0002 0001 0000 0003
(not powered
in Standby)
1 RTCCLK
RTC_CNT FFFFFFFB
FFFFFFFC
RTC_PR
0002 0001 0000 0003 0002 0001 0000 0003
FFFFFFFD
RTC_Overflow
0002 0001 0000 0003
FFFFFFFE
0002 0001 0000 0003
FFFFFFFF
0002 0001 0000 0003
OWF
can be cleared by software
RTC_Second
RTCCLK
0000
0002 0001 0000 0003
(not powered
in Standby)
1 RTCCLK

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English