ST STM32F101xx User Manual

RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 12 137/1096
8.3.4 APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
1514131211109 8 76543210
Res.
USART1
RST
Res.
SPI1
RST
TIM1
RST
ADC2
RST
ADC1
RST
Reserved
IOPE
RST
IOPD
RST
IOPC
RST
IOPB
RST
IOPA
RST
Res.
AFIO
RST
rw rw rw rw rw rw rw rw rw rw rw
Bits 31:15 Reserved, always read as 0.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, always read as 0.
Bit 12 SPI1RST: SPI 1 reset
Set and cleared by software.
0: No effect
1: Reset SPI 1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 ADC2RST: ADC 2 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 2 interface
Bit 9 ADC1RST: ADC 1 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 1 interface
Bits 8:7 Reserved, always read as 0.
Bit 6 IOPERST: I/O port E reset
Set and cleared by software.
0: No effect
1: Reset I:O port E
Bit 5 IOPDRST: I/O port D reset
Set and cleared by software.
0: No effect
1: Reset I/O port D

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English