ST STM32F101xx User Manual

Flexible static memory controller (FSMC) RM0008
510/1096 Doc ID 13902 Rev 12
Table 119. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-16 0x0000
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13-10 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 -
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP As needed
1 MUXEN 0x0
0 MBKEN 0x1
Table 120. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x2
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) in
read. This value cannot be 0 (minimum is 1)
7-4 ADDHLD
Duration of the middle phase of the read access (ADDHLD+1 HCLK
cycles)
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) in
read.
Table 121. FSMC_BWTRx bit fields
Bit No. Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x2
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles) in
write. This value cannot be 0 (minimum is 1)
7-4 ADDHLD
Duration of the middle phase of the write access (ADDHLD+1 HCLK
cycles)
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in write.

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English