General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008
186/1096 Doc ID 13902 Rev 12
9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2)
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15141312111098765 4 3210
Reserved
FSMC_
NADV
TIM14_
REMAP
TIM13_
REMAP
TIM11_
REMAP
TIM10_
REMAP
TIM9_R
EMAP
Reserved
rw rw rw rw rw rw
Bits 31:11 Reserved.
Bit 10 FSMC_NADV: NADV connect/disconnect
This bit is set and cleared by software. It controls the use of the optional FSMC_NADV
signal.
0: The NADV signal is connected to the output (default)
1: The NADV signal is not connected. The I/O pin can be used by another peripheral.
Bit 9 TIM14_REMAP: TIM14 remapping
This bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate
function onto the GPIO ports.
0: No remap (PA7)
1: Remap (PF9)
Bit 8 TIM13_REMAP: TIM13 remapping
This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate
function onto the GPIO ports.
0: No remap (PA6)
1: Remap (PF8)
Bit 7 TIM11_REMAP: TIM11 remapping
This bit is set and cleared by software. It controls the mapping of the TIM11_CH1 alternate
function onto the GPIO ports.
0: No remap (PB9)
1: Remap (PF7)
Bit 6 TIM10_REMAP: TIM10 remapping
This bit is set and cleared by software. It controls the mapping of the TIM10_CH1 alternate
function onto the GPIO ports.
0: No remap (PB8)
1: Remap (PF6)
Bit 5 TIM9_REMAP: TIM9 remapping
This bit is set and cleared by software. It controls the mapping of the TIM9_CH1 and
TIM9_CH2 alternate functions onto the GPIO ports.
0: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3)
1: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6)
Bits 4:0 Reserved.
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