ST STM32F101xx User Manual

Revision history RM0008
1082/1096 Doc ID 13902 Rev 12
08-Feb-2008 3
Figure 4: Power supply overview on page 66 modified.
Section 7.1.2: Power reset on page 88 modified.
Section 7.2: Clocks on page 89 modified.
Definition of Bits 26:24 modified in Section 9.4.2: AF remap and debug I/O configuration
register (AFIO_MAPR) on page 178.
AFIO_EVCR bits corrected in Table 60: AFIO register map and reset values on page 187.
Number of maskable interrupt channels modified in Section 10.1: Nested vectored
interrupt controller (NVIC) on page 189
.
Section 13.3.6: Interrupts on page 269 added. Small text changes.
Examples modified in Figure 91: 6-step generation, COM example (OSSR=1) on
page 310.
Table 83: Output control bits for complementary OCx and OCxN channels with break
feature on page 337 modified.
Register names modified in Section 24.9.4: CAN filter registers on page 667.
Small text change in Section 26.3.3: I2C master mode on page 731.
Bits 5:0 frequency description modified in Section 26.6.2: Control register 2 (I2C_CR2) on
page 749.
Section 23.3.1: Description of USB blocks on page 601 modified.
Section 25.3.4: Configuring the SPI for Simplex communication on page 683 modified.
Section 25.3.6: CRC calculation on page 690 modified.
Note added in BUSY flag on page 692.
Section 25.3.8: Disabling the SPI on page 693 added.
Appendix A: Important notes, removed.
22-May-2008
4
continued
on next
page
Reference manual updated to apply to devices containing up to 512 Kbytes of Flash
memory (High-density devices). Document restructured. Small text changes. Definitions of
Medium-density and High-density devices added to all sections.
In Section 3: Memory and bus architecture on page 47:
– Figure 1: System architecture on page 47, Figure 2: Memory map on page 39, Ta bl e 3 :
Register boundary addresses on page 50 updated
– Note and text added to AHB/APB bridges (APB) on page 49
– SRAM size in Section 3.3.1: Embedded SRAM on page 53
– Section 3.3.3: Embedded Flash memory on page 54 updated (Flash size, page size,
number of pages, Reading the Flash memory, Table 6: Flash module organization (high-
density devices) on page 56 added)
– Prefetch buffer on/off specified in Reading the Flash memory
bit_number definition modified in Section 3.3.2: Bit banding on page 53.
Section 4: CRC calculation unit on page 62 added (Table 3: Register boundary addresses
on page 50 updated, Figure 2: Memory map on page 39 updated and CRCEN bit added to
Section 7.3.6: AHB peripheral clock enable register (RCC_AHBENR) on page 108).
Entering Stop mode on page 72 specified.
Updated in Section 6: Backup registers (BKP) on page 79: number of backup registers and
available storage size and Section 6.1: BKP introduction. ASOE definition modified in
Section 6.4.2: RTC clock calibration register (BKP_RTCCR) on page 81.
Table 232. Document revision history (continued)
Date Revision Changes

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English