RM0008 Flexible static memory controller (FSMC)
Doc ID 13902 Rev 12 513/1096
1. Memory asserts the WAIT signal aligned to NOE/NWE which toggles:
data_setup phase >= 4 * HCLK + max_wait_assertion_time
2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling) :
if max_wait_assertion_time > (address_phase + hold_phase)
data_setup phase >= 4 * HCLK + (max_wait_assertion_time - address_phase -
hold_phase)
otherwise
data_setup phase >= 4 * HCLK
Where max_wait_assertion_time is the maximum time taken by the memory to assert the
WAIT signal once NEx/NOE/NWE is low.
The Figure 199 and Figure 200 show the number of HCLK clock cycles that memory
access is extended after WAIT is removed by the asynchronous memory (independently of
the above cases).
Figure 199. Asynchronous wait during a read access
A[25:0]
NOE
(#,+
Memory transaction
.7!)4
D[15:0]
.%X
DATADRIVEN
BYMEMORY
AI
ADDRESSPHASE
DONTCARE
DATA?SETUPPHASE
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