RM0008 Flexible static memory controller (FSMC)
Doc ID 13902 Rev 12 491/1096
The effect of this AHB error depends on the AHB master which has attempted the R/W
access:
● If it is the Cortex™-M3 CPU, a hard fault inetrrupt is generated
● If is is a DMA, a DMA transfer error is generated and the corresponding DMA channel
is automatically disabled.
The AHB clock (HCLK) is the reference clock for the FSMC.
21.3.1 Supported memories and transactions
General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
● AHB transaction size and memory data size are equal
There is no issue in this case.
● AHB transaction size is greater than the memory size
In this case, the FSMC splits the AHB transaction into smaller consecutive memory
accesses in order to meet the external data width.
● AHB transaction size is smaller than the memory size
Asynchronous transfers may or not be consistent depending on the type of external
device.
– Asynchronous accesses to devices that have the byte select feature (SRAM,
ROM, PSRAM).
In this case, the FSMC allows read/write transactions and accesses the right data
through its byte lanes BL[1:0]
– Asynchronous accesses to devices that do not have the byte select feature (NOR
and NAND Flash 16-bit).
This situation occurs when a byte access is requested to a 16-bit wide Flash
memory. Clearly, the device cannot be accessed in byte mode (only 16-bit words
can be read from/written to the Flash memory) therefore:
a) Write transactions are not allowed
b) Read transactions are allowed (the controller reads the entire 16-bit memory word
and uses the needed byte only).
Configuration registers
The FSMC can be configured using a register set. See Section 21.5.6, for a detailed
description of the NOR Flash/PSRAM controller registers. See Section 21.6.8, for a detailed
description of the NAND Flash/PC Card registers.
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