Window watchdog (WWDG) RM0008
484/1096 Doc ID 13902 Rev 12
20.4 How to program the watchdog timeout
You can use the formula in Figure 184 to calculate the WWDG timeout.
Warning: When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 184. Window watchdog timing diagram
20.5 Debug mode
When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter
either continues to work normally or stops, depending on DBG_WWDG_STOP configuration
bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,
watchdog, bxCAN and I2C.
T6 bit
Reset
W[6:0]
T[6:0] CNT downcounter
time
Refresh windowRefresh not allowed
0x3F
The formula to calculate the timeout value is given by:
where:
T
WWDG
: WWDG timeout
T
PCLK1
: APB1 clock period measured in ms
Min-max timeout value @36 MHz (PCLK1)
WDGTB Min timeout value Max timeout value
0 113 µs 7.28 ms
1 227 µs 14.56 ms
2 455 µs 29.12 ms
3 910 µs 58.25 ms
T
WWDG
T
PCLK1
4096× 2
WDGTB
× T5:0[]1+()×= ms()
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