RM0008 Flexible static memory controller (FSMC)
Doc ID 13902 Rev 12 489/1096
● Write enable and byte lane select outputs for use with PSRAM and SRAM devices
● Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to
external 16-bit or 8-bit devices
● A Write FIFO, 2 words long, each word is 32 bits wide, only stores data and not the
address. Therefore, this FIFO only buffers AHB write burst transactions. This makes it
possible to write to slow memories and free the AHB quickly for other operations. Only
one burst at a time is buffered: if a new AHB burst or single transaction occurs while an
operation is in progress, first the FIFO is drained ( The FSMC will insert wait states until
the current memory access is complete).
● External asynchronous wait control
The FSMC registers that define the external device type and associated characteristics are
usually set at boot time and do not change until the next reset or power-up. However, it is
possible to change the settings at any time.
21.2 Block diagram
The FSMC consists of four main blocks:
● The AHB interface (including the FSMC configuration registers)
● The NOR Flash/PSRAM controller
● The NAND Flash/PC Card controller
● The external device interface
The block diagram is shown in Figure 185.
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