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USB on-the-go full-speed (OTG_FS) RM0008

852/1096 Doc ID 13902 Rev 12

OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx)

(x = 1..3, where x is the FIFO_number)

Address offset: 0x104 + (FIFO_number – 1) × 0x04

Reset value: 0x02000400

28.16.3 Host-mode registers

Bit values in the register descriptions are expressed in binary unless otherwise specified.

Host-mode registers affect the operation of the core in the host mode. Host mode registers

must not be accessed in device mode, as the results are undefined. Host mode registers

can be categorized as follows:

OTG_FS Host configuration register (OTG_FS_HCFG)

Address offset: 0x400

Reset value: 0x0000 0000

This register configures the core after power-on. Do not make changes to this register after

initializing the host.

313029282726252423222120191817161514131211109876543210

INEPTXFD INEPTXSA

r/r

Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth

This value is in terms of 32-bit words.

Minimum value is 16

The power-on reset value of this register is specified as the largest IN endpoint FIFO number

depth.

Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address

This field contains the memory start address for IN endpoint transmit FIFOx.

313029282726252423222120191817161514131211109876543210

Reserved

FSLSS

FSLSPCS

rrwrw

Bits 31:3 Reserved

Bit 2 FSLSS: FS- and LS-only support

The application uses this bit to control the core’s enumeration speed. Using this bit, the

application can make the core enumerate as an FS host, even if the connected device

supports HS traffic. Do not make changes to this field after initial programming.

1: FS/LS-only, even if the connected device can support HS (read-only)

ST STM32F101xx User Manual

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