Memory and bus architecture RM0008
48/1096 Doc ID 13902 Rev 12
In connectivity line devices the main system consists of:
● Five masters:
– Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
– GP-DMA1 & 2 (general-purpose DMA)
– Ethernet DMA
● Three slaves:
– Internal SRAM
– Internal Flash memory
– AHB to APB bridges (AHB to APBx), which connect all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 2:
Figure 2. System architecture in connectivity line devices
ICode bus
This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
FLITF
Ch.1
Ch.2
Ch.7
Cortex-M3
DMA1
ICode
DCode
System
DMA request
APB1
Flash
Bridge 2
Bridge 1
Ch.1
Ch.2
Ch.5
DMA2
SRAM
APB2
GPIOC
USART1
SPI1
TIM1
ADC2
ADC1
GPIOE
GPIOD
GPIOB
GPIOA
EXTI
AFIO
DAC
SPI3/I2S
TIM2
PWR
BKP
CAN1
CAN2
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI2/I2S
IWDG
WWDG
RTC
TIM7
TIM6
TIM5
TIM4
TIM3
ai15810
Bus matrix
DMA
DMA
Reset & clock
control (RCC)
USB OTG FS
AHB system bus
Ethernet MAC
DMA
DMA request
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