ST STM32F101xx User Manual

Inter-integrated circuit (I
2
C) interface RM0008
756/1096 Doc ID 13902 Rev 12
26.6.8 Clock control register (I2C_CCR)
Address offset: 0x1C
Reset value: 0x0000
Note: 1 To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral input clock)
must be a multiple of 10 MHz.
2 The CCR register must be configured only when the I2C is disabled (PE = 0).
Bit 0 MSL: Master/slave
0: Slave Mode
1: Master Mode
–Set by hardware as soon as the interface is in Master mode (SB=1).
–Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
(ARLO=1), or by hardware when PE=0.
151413121110987 654321 0
F/S DUTY
Reserved
CCR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit 15 F/S: I2C master mode selection
0: Standard Mode I2C
1: Fast Mode I2C
Bit 14 DUTY: Fast mode duty cycle
0: Fast Mode t
low
/t
high
= 2
1: Fast Mode t
low
/t
high
= 16/9 (see CCR)
Bits 13:12 Reserved, forced by hardware to 0.
Bits 11:0 CCR[11:0]: Clock control register in Fast/Standard mode (Master mode)
Controls the SCL clock in master mode.
Standard mode or SMBus
:
T
high
= CCR * T
PCLK1
T
low
= CCR * T
PCLK1
Fast mode:
If DUTY = 0:
T
high
= CCR * T
PCLK1
T
low
= 2 * CCR * T
PCLK1
If DUTY = 1: (to reach 400 kHz)
T
high
= 9 * CCR * T
PCLK1
T
low
= 16 * CCR * T
PCLK1
For instance: in standard mode, to generate a 100 kHz SCL frequency:
If FREQR = 08, T
PCLK1
= 125 ns so CCR must be programmed with 0x28
(0x28 <=> 40d x 125 ns = 5000 ns.)
Note: 1. The minimum allowed value is 0x04, except in FAST DUTY mode where the
minimum allowed value is 0x01
2. t
high
= t
r(SCL)
+ t
w(SCLH)
. See device datasheet for the definitions of parameters
3. t
low
= t
f(SCL)
+ t
w(SCLL)
. See device datasheet for the definitions of parameters
4. These timings are without filters.
5. The CCR register must be configured only when the I
2
C is disabled (PE = 0).

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English