ST STM32F101xx

RM0008 General-purpose timers (TIM2 to TIM5)
Doc ID 13902 Rev 12 353/1096
Figure 106. Counter timing diagram, internal clock divided by N
Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
Timer clock = CK_CNT
Counter register
00
1F
20
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
CK_INT
00
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 0732 33 34 35 3631
Auto-reload register
FF 36
Write a new value in TIMx_ARR
CK_INT