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ST STM32F101xx User Manual

ST STM32F101xx
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USB on-the-go full-speed (OTG_FS) RM0008
810/1096 Doc ID 13902 Rev 12
When a resume signaling is detected from the host, the resume interrupt (RWUSIG bit in
OTG_FS_GINTSTS) is generated and the device suspend bit is automatically cleared.
28.5.3 Peripheral endpoints
The OTG_FS core instantiates the following USB endpoints:
Control endpoint 0:
Bidirectional and handles control messages only
Separate set of registers to handle in and out transactions
Proper control (OTG_FS_DIEPCTL0/OTG_FS_DOEPCTL0), transfer
configuration (OTG_FS_DIEPTSIZ0/OTG_FS_DIEPTSIZ0), and status-interrupt
(OTG_FS_DIEPINTx/)OTG_FS_DOEPINT0) registers. The available set of bits
inside the control and transfer size registers slightly differs from that of other
endpoints
3 IN endpoints
Each of them can be configured to support the isochronous, bulk or interrupt
transfer type
Each of them has proper control (OTG_FS_DIEPCTLx), transfer configuration
(OTG_FS_DIEPTSIZx), and status-interrupt (OTG_FS_DIEPINTx) registers
The Device IN endpoints common interrupt mask register (OTG_FS_DIEPMSK) is
available to enable/disable a single kind of endpoint interrupt source on all of the
IN endpoints (EP0 included)
Support for incomplete isochronous IN transfer interrupt (IISOIXFR bit in
OTG_FS_GINTSTS), asserted when there is at least one isochronous IN endpoint
on which the transfer is not completed in the current frame. This interrupt is
asserted along with the end of periodic frame interrupt
(OTG_FS_GINTSTS/EOPF).
3 OUT endpoints
Each of them can be configured to support the isochronous, bulk or interrupt
transfer type
Each of them has a proper control (OTG_FS_DOEPCTLx), transfer configuration
(OTG_FS_DOEPTSIZx) and status-interrupt (OTG_FS_DOEPINTx) register
Device Out endpoints common interrupt mask register (OTG_FS_DOEPMSK) is
available to enable/disable a single kind of endpoint interrupt source on all of the
OUT endpoints (EP0 included)
Support for incomplete isochronous OUT transfer interrupt (INCOMPISOOUT bit
in OTG_FS_GINTSTS), asserted when there is at least one isochronous OUT
endpoint on which the transfer is not completed in the current frame. This interrupt
is asserted along with the end of periodic frame interrupt
(OTG_FS_GINTSTS/EOPF).

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ST STM32F101xx Specifications

General IconGeneral
BrandST
ModelSTM32F101xx
CategoryMicrocontrollers
LanguageEnglish

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