ST STM32F101xx User Manual

RM0008 General-purpose timers (TIM2 to TIM5)
Doc ID 13902 Rev 12 401/1096
15.4.13 TIMx capture/compare register 1 (TIMx_CCR1)
Address offset: 0x34
Reset value: 0x0000
15.4.14 TIMx capture/compare register 2 (TIMx_CCR2)
Address offset: 0x38
Reset value: 0x0000
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CCR1[15:0]
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Bits 15:0 CCR1[15:0]: Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
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CCR2[15:0]
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Bits 15:0 CCR2[15:0]: Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English