Backup registers (BKP) RM0008
82/1096 Doc ID 13902 Rev 12
6.4.3 Backup control register (BKP_CR)
Address offset: 0x30
Reset value: 0x0000 0000
Note: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at
the same time can generate a spurious Tamper event. For this reason it is recommended to
change the TPAL bit only when the TPE bit is reset.
6.4.4 Backup control/status register (BKP_CSR)
Address offset: 0x34
Reset value: 0x0000 0000
Bit 6:0 CAL[6:0]: Calibration value
This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses.
This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20
PPM.
The clock of the RTC can be slowed down from 0 to 121PPM.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TPAL TPE
rw rw
Bits 15:2 Reserved, always read as 0.
Bit 1 TPAL: TAMPER pin active level
0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set).
1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).
Bit 0 TPE: TAMPER pin enable
0: The TAMPER pin is free for general purpose I/O
1: Tamper alternate I/O function is activated.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TIF TEF
Reserved
TPIE CTI CTE
rr rwww
Bits 15:10 Reserved, always read as 0.
Bit 9 TIF: Tamper interrupt flag
This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is
cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is
reset.
0: No Tamper interrupt
1: A Tamper interrupt occurred
Note: This bit is reset only by a system reset and wakeup from Standby mode.
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