RM0008 Serial peripheral interface (SPI)
Doc ID 13902 Rev 12 699/1096
The I
2
S interface supports four audio standards, configurable using the I2SSTD[1:0] and
PCMSYNC bits in the SPI_I2SCFGR register.
I
2
S Phillips standard
For this standard, the WS signal is used to indicate which channel is being transmitted. It is
activated one CK clock cycle before the first bit (MSB) is available.
Figure 249. I
2
S Phillips protocol waveforms (16/32-bit full accuracy, CPOL = 0)
Data are latched on the falling edge of CK (for the transmitter) and are read on the rising
edge (for the receiver). The WS signal is also latched on the falling edge of CK.
Figure 250. I
2
S Phillips standard waveforms (24-bit frame with CPOL = 0)
This mode needs two write or read operations to/from the SPI_DR.
● In transmission mode:
if 0x8EAA33 has to be sent (24-bit):
MSB
LSB
MSB
CK
WS
SD
Channel left
Channel right
May be 16-bit, 32-bit
Transmission
Reception
CK
WS
SD
Channel left 32-bit
Channel right
MSB LSB
8-bit remaining
0 forced
24-bit data
Transmission
Reception
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