RM0008 Inter-integrated circuit (I
2
C) interface
Doc ID 13902 Rev 12 757/1096
26.6.9 TRISE register (I2C_TRISE)
Address offset: 0x20
Reset value: 0x0002
151413121110987 654321 0
Reserved
TRISE[5:0]
rw rw rw rw rw rw
Bits 15:6 Reserved, forced by hardware to 0.
Bits 5:0 TRISE[5:0]: Maximum rise time in Fast/Standard mode (Master mode)
These bits must be programmed with the maximum SCL rise time given in the I
2
C bus
specification, incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 0x08 and T
PCLK1
= 125 ns
therefore the TRISE[5:0] bits must be programmed with 09h.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order
to respect the t
HIGH
parameter.
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
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