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Power control (PWR) RM0008

74/1096 Doc ID 13902 Rev 12

Entering Standby mode

Refer to Ta bl e 1 5 for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control

bits:

● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by

hardware option. Once started it cannot be stopped except by a reset. See

Section 19.3: IWDG functional description in Section 19: Independent watchdog

(IWDG).

● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control

● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status

● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the

Backup domain control register (RCC_BDCR)

Exiting Standby mode

The microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG

reset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see

Figure 179: RTC simplified block diagram). All registers are reset after wakeup from

Standby except for Power control/status register (PWR_CSR).

After waking up from Standby mode, program execution restarts in the same way as after a

Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power

control/status register (PWR_CSR) indicates that the MCU was in Standby mode.

Refer to Ta bl e 1 5 for more details on how to exit Standby mode.

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except:

● Reset pad (still available)

● TAMPER pin if configured for tamper or calibration out

● WKUP pin, if enabled

Table 15. Standby mode

Standby mode Description

Mode entry

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– Set SLEEPDEEP in Cortex™-M3 System Control register

– Set PDDS bit in Power Control register (PWR_CR)

– Clear WUF bit in Power Control/Status register (PWR_CSR)

Mode exit

WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in

NRST pin, IWDG Reset.

Wakeup latency Reset phase

ST STM32F101xx User Manual

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