ST STM32F101xx User Manual

RM0008 Flexible static memory controller (FSMC)
Doc ID 13902 Rev 12 503/1096
Table 111. FSMC_BTRx bit fields
Bit
number
Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x0
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) in
read. This value cannot be 0 (minimum is 1)
7-4 0x0
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read.
Table 112. FSMC_BWTRx bit fields
Bit
number
Bit name Value to set
31-30 0x0
29-28 ACCMOD 0x0
27-16 0x000
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles) in
write. This value cannot be 0 (minimum is 1).
7-4 0x0
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) in write

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English