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Ethernet (ETH): media access control (MAC) with DMA controller RM0008

960/1096 Doc ID 13902 Rev 12

MII/RMII transmit timing diagrams

Figure 338. Transmission with no collision

Figure 339. Transmission with collision

Figure 340 shows a frame transmission in MII and RMII.

MII_TX_CLK

MII_TX_EN

MII _TXD[3:0]

PR EA MB LE

MII_CS

MII_COL

ai15631

Low

MII_TX_CLK

MII_TX_EN

MII _TXD[3:0]

PR EAM BLE SFD

MII_CS

MII_COL

ai15651

DA DA JAM JAM JAM JAM

Main Page

Default Chapter2
- Table of Contents2
Overview of the Manual40
- Table 1. Sections Related to each Stm32F10Xxx Product40
- Table40
- Table 2. Sections Related to each Peripheral43
Documentation Conventions46
- List of Abbreviations for Registers46
- Glossary46
- Peripheral Availability46
Memory and Bus Architecture47
- System Architecture47
- Figure 1. System Architecture47
- Figure 2. System Architecture in Connectivity Line Devices48
- Memory Organization49
- Memory Map50
- Table54
- Boot Configuration60
- Table 9. Boot Modes60
CRC Calculation Unit62
- CRC Introduction62
- CRC Main Features62
- Figure 3. CRC Calculation Unit Block Diagram62
- CRC Functional Description63
- CRC Registers63
Power Control (PWR)65
- Power Supplies65
- Power Supply Supervisor68
- Low-Power Modes70
- Power Control Registers75
Backup Registers (BKP)79
- BKP Introduction79
- BKP Main Features79
- BKP Functional Description80
  - Tamper Detection80
  - RTC Calibration80
- BKP Registers81
Low-, Medium-, High- and XL-Density Reset and Clock Control (RCC)87
- Reset87
- Clocks89
- RCC Registers96
Connectivity Line Devices: Reset and Clock Control (RCC)120
- Reset120
- Clocks122
- RCC Registers129
General-Purpose and Alternate-Function I/Os (Gpios and Afios)154
- GPIO Functional Description154
- Usarts161
- Figure 18. High Impedance-Analog Configuration161
- Table 25. SPI162
- Table 26. I2S162
- Table 27. I2C163
- Table 28. Bxcan163
- Usb163
- Table 30. OTG_FS Pin Configuration163
- Sdio164
- Fsmc164
- AFIO Registers176
- GPIO and AFIO Register Maps187
- Table 59. GPIO Register Map and Reset Values187
- Table 60. AFIO Register Map and Reset Values187
Interrupts and Events189
- Nested Vectored Interrupt Controller (NVIC)189
- External Interrupt/Event Controller (EXTI)197
- EXTI Registers201
Analog-To-Digital Converter (ADC)205
- ADC Introduction205
- ADC Main Features206
- ADC Functional Description206
  - Figure 22. Single ADC Block Diagram207
  - Table 65. ADC Pins208
  - ADC Clock209
  - ADC On-Off Control209
  - Channel Selection209
  - Single Conversion Mode209
  - Continuous Conversion Mode210
  - Figure 23. Timing Diagram210
  - Timing Diagram210
  - Analog Watchdog211
  - Figure 24. Analog Watchdog Guarded Area211
  - Scan Mode211
  - Table 66. Analog Watchdog Channel Selection211
  - Figure 25. Injected Conversion Latency212
  - Injected Channel Management212
  - Discontinuous Mode213
- Calibration213
- Data Alignment214
- Figure 26. Calibration Timing Diagram214
- Figure 27. Right Alignment of Data214
- Figure 28. Left Alignment of Data214
- Channel-By-Channel Programmable Sample Time215
- Conversion on External Trigger215
- Table 67. External Trigger for Regular Channels for ADC1 and ADC2215
- Table 68. External Trigger for Injected Channels for ADC1 and ADC2216
- Table 69. External Trigger for Regular Channels for ADC3216
- Table 70. External Trigger for Injected Channels for ADC3216
- DMA Request217
- Dual ADC Mode218
  - Figure 29. Dual ADC Block Diagram219
  - Figure 30. Injected Simultaneous Mode on 4 Channels220
  - Injected Simultaneous Mode220
  - Regular Simultaneous Mode220
  - Fast Interleaved Mode221
  - Figure 31. Regular Simultaneous Mode on 16 Channels221
  - Figure 32. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode221
  - Slow Interleaved Mode221
  - Alternate Trigger Mode222
  - Figure 33. Slow Interleaved Mode on 1 Channel222
  - Figure 34. Alternate Trigger: Injected Channel Group of each ADC222
  - Combined Regular Simultaneous + Alternate Trigger Mode223
  - Combined Regular/Injected Simultaneous Mode223
  - Figure 35. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model223
  - Independent Mode223
  - Combined Injected Simultaneous + Interleaved224
  - Figure 36. Alternate + Regular Simultaneous224
  - Figure 37. Case of Trigger Occurring During Injected Conversion224
  - Figure 38. Interleaved Single Channel with Injected Sequence CH11, CH12224
- Temperature Sensor225
- Figure 39. Temperature Sensor and VREFINT Channel Block Diagram225
- ADC Interrupts226
- Table 71. ADC Interrupts226
- ADC Registers227
  - ADC Status Register (ADC_SR)227
  - ADC Control Register 1 (ADC_CR1)228
  - ADC Control Register 2 (ADC_CR2)230
  - ADC Sample Time Register 1 (ADC_SMPR1)234
  - ADC Sample Time Register 2 (ADC_SMPR2)235
  - ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1235
  - ADC Watchdog High Threshold Register (ADC_HTR)236
  - ADC Watchdog Low Threshold Register (ADC_LTR)236
  - ADC Regular Sequence Register 1 (ADC_SQR1)237
  - ADC Regular Sequence Register 2 (ADC_SQR2)238
  - ADC Regular Sequence Register 3 (ADC_SQR3)239
  - ADC Injected Sequence Register (ADC_JSQR)240
  - ADC Injected Data Register X (Adc_Jdrx) (X= 1240
  - ADC Regular Data Register (ADC_DR)241
  - 11.12.15 ADC Register Map241
  - Table 72. ADC Register Map and Reset Values241
Digital-To-Analog Converter (DAC)243
- DAC Introduction243
- DAC Main Features243
- Table 73. DAC Pins244
- Figure 40. DAC Channel Block Diagram244
- DAC Functional Description245
- Dual DAC Channel Conversion250
- DAC Registers254
DMA Controller (DMA)263
- DMA Introduction263
- DMA Main Features263
- Figure 48. DMA Block Diagram in Connectivity Line Devices264
- DMA Functional Description265
- DMA Registers273
Advanced-Control Timers (TIM1&TIM8)280
- TIM1&TIM8 Introduction280
- TIM1&TIM8 Main Features281
- Figure 52. Advanced-Control Timer Block Diagram282
- TIM1&TIM8 Functional Description283
- TIM1&TIM8 Registers321
General-Purpose Timers (TIM2 to TIM5)347
- TIM2 to TIM5 Introduction347
- Timx Main Features348
- Timx Functional Description349
- Timx2 to TIM5 Registers384
General-Purpose Timers (TIM9 to TIM14)408
- TIM9 to TIM14 Introduction408
- TIM9 to TIM14 Main Features409
  - TIM9/TIM12 Main Features409
  - Figure 146. General-Purpose Timer Block Diagram (TIM9 and TIM12)409
- TIM10/TIM11 and TIM13/TIM14 Main Features410
- Figure 147. General-Purpose Timer Block Diagram (TIM10/11/13/14)410
- TIM9 to TIM14 Functional Description411
- TIM9 and TIM12 Registers429
- TIM10/11/13/14 Registers442
Basic Timers (TIM6&TIM7)452
- TIM6&TIM7 Introduction452
- TIM6&TIM7 Main Features452
- TIM6&TIM7 Functional Description453
- TIM6&TIM7 Registers458
Real-Time Clock (RTC)464
- RTC Introduction464
- RTC Main Features465
- RTC Functional Description466
- RTC Registers469
Independent Watchdog (IWDG)476
- IWDG Introduction476
- IWDG Main Features476
- IWDG Functional Description476
- IWDG Registers479
Window Watchdog (WWDG)482
- WWDG Introduction482
- WWDG Main Features482
- WWDG Functional Description482
- Figure 183. Watchdog Block Diagram483
- How to Program the Watchdog Timeout484
- Debug Mode484
- Figure 184. Window Watchdog Timing Diagram484
- WWDG Registers485
Flexible Static Memory Controller (FSMC)488
- FSMC Main Features488
- Block Diagram489
- AHB Interface490
  - Figure 185. FSMC Block Diagram490
  - Supported Memories and Transactions491
- External Device Address Mapping492
- NOR Flash/Psram Controller494
- NAND Flash/Pc Card Controller526
Secure Digital Input/Output Interface (SDIO)543
- SDIO Main Features543
- SDIO Bus Topology544
- Figure 206. SDIO "No Response" and "No Data" Operations544
- Figure 207. SDIO (Multiple) Block Read Operation544
- Figure 208. SDIO (Multiple) Block Write Operation545
- Figure 209. SDIO Sequential Read Operation545
- Figure 210. SDIO Sequential Write Operation545
- SDIO Functional Description546
- Card Functional Description558
- Response Formats577
- SDIO I/O Card-Specific Operations581
- CE-ATA Specific Operations582
- HW Flow Control583
- SDIO Registers583
Universal Serial Bus Full-Speed Device Interface (USB)599
- USB Introduction599
- USB Main Features599
- USB Functional Description599
  - Figure 219. USB Peripheral Block Diagram600
  - Description of USB Blocks601
- Programming Considerations602
- USB Registers613
Controller Area Network (Bxcan)630
- Bxcan Introduction630
- Bxcan Main Features630
- Bxcan General Description631
- Bxcan Operating Modes633
- Test Mode635
- Stm32F10Xxx in Debug Mode637
- Bxcan Functional Description637
- Bxcan Interrupts648
- Figure 234. CAN Frames648
- Figure 235. Event Flags and Interrupt Generation649
- CAN Registers650
Serial Peripheral Interface (SPI)674
- SPI Introduction674
- SPI and I 2 S Main Features675
  - SPI Features675
  - I 2 S Features676
- SPI Functional Description677
- S Functional Description697
- (Connectivity Line Devices Only)708
- SPI and I 2 S Registers716
Inter-Integrated Circuit (I 2 C) Interface726
- I 2 C Introduction726
- I 2 C Main Features726
- I 2 C Functional Description727
- I 2 C Interrupts745
- Table 188. I2C Interrupt Requests745
- Figure 277. I2C Interrupt Mapping Diagram746
- I 2 C Debug Mode747
- I 2 C Registers747
Universal Synchronous Asynchronous Receiver Transmitter (USART)759
- USART Introduction759
- USART Main Features760
- USART Functional Description761
- USART Interrupts790
- Figure 299. CTS Flow Control790
- USART Mode Configuration791
- USART Registers791
USB On-The-Go Full-Speed (OTG_FS)802
- OTG_FS Introduction802
- OTG_FS Main Features803
- OTG_FS Functional Description805
- OTG Dual Role Device (DRD)806
- USB Peripheral808
- USB Host812
- SOF Trigger817
- Power Options818
- Dynamic Update of the OTG_FS_HFIR Register819
- USB Data Fifos819
- Figure 306. Updating OTG_FS_HFIR Dynamically819
- Peripheral FIFO Architecture820
- Host FIFO Architecture821
- FIFO RAM Allocation822
  - Device Mode822
  - Host Mode823
- USB System Performance823
- OTG_FS Interrupts824
- Figure 309. Interrupt Hierarchy825
- OTG_FS Control and Status Registers826
- OTG_FS Programming Model892
Ethernet (ETH): Media Access Control (MAC) with DMA Controller938
- Ethernet Introduction938
- Ethernet Main Features938
- Ethernet Pins941
- Table 205. Ethernet Pin Configuration941
- Ethernet Functional Description: SMI, MII and RMII942
- Ethernet Functional Description: MAC 802.3950
- Ethernet Functional Description: DMA Controller Operation979
- Error Response to DMA982
Device Electronic Signature1045
- Memory Size Registers1045
  - Flash Size Register1045
- Unique Device ID Register (96 Bits)1046
Debug Support (DBG)1048
- Overview1048
  - Cortex-M3-Level Debug Support1049
  - Figure 359. Block Diagram of Stm32F10Xxx-Level and1049
- Reference ARM Documentation1050
- SWJ Debug Port (Serial Wire and JTAG)1050
  - Mechanism to Select the JTAG-DP or the SW-DP1050
  - Figure 360. SWJ Debug Port1050
- Pinout and Debug Port Pins1051
  - SWJ Debug Port Pins1052
  - Flexible SWJ-DP Pin Assignment1052
  - Table 215. SWJ Debug Port Pins1052
  - Internal Pull-Up and Pull-Down on JTAG Pins1053
  - Table 216. Flexible SWJ-DP Pin Assignment1053
  - Using Serial Wire and Releasing the Unused Debug Pins as Gpios1054
- Stm32F10Xxx JTAG TAP Connection1054
- ID Codes and Locking Mechanism1055
  - MCU Device ID Code1055
  - Figure 361. JTAG TAP Connections1055
  - Boundary Scan TAP1056
  - Cortex-M3 TAP1057
  - Cortex-M3 JEDEC-106 ID Code1057
- JTAG Debug Port1057
- Table 217. JTAG Debug Port Data Registers1057
- Table 218. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]1058
- SW Debug Port1059
  - SW Protocol Introduction1059
  - SW Protocol Sequence1059
  - Table 219. Packet Request (8-Bits)1059
  - SW-DP State Machine (Reset, Idle States, ID Code)1060
  - DP and AP Read/Write Accesses1060
  - Table 220. ACK Response (3 Bits)1060
  - Table 221. DATA Transfer (33 Bits)1060
  - SW-DP Registers1061
  - SW-AP Registers1061
  - Table 222. SW-DP Registers1061
- AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP1062
- Table 223. Cortex-M3 AHB-AP Registers1062
- Capability of the Debugger Host to Connect under System Reset1063
- Core Debug1063
- Table 224. Core Debug Registers1063
- DWT (Data Watchpoint Trigger)1064
- FPB (Flash Patch Breakpoint)1064
- ITM (Instrumentation Trace Macrocell)1065
  - General Description1065
  - Time Stamp Packets, Synchronization and Overflow Packets1065
  - Table 225. Main ITM Registers1066
- ETM (Embedded Trace Macrocell)1067
  - General Description1067
  - Signal Protocol, Packet Types1067
  - Main ETM Registers1067
  - Table 226. Main ETM Registers1067
  - Configuration Example1068
- MCU Debug Component (DBGMCU)1068
  - Debug Support for Low-Power Modes1068
  - Debug Support for Timers, Watchdog, Bxcan and I C1068
  - Debug MCU Configuration Register1069
- TPIU (Trace Port Interface Unit)1072
  - Introduction1072
  - TRACE Pin Assignment1072
  - Table 227. Asynchronous TRACE Pin Assignment1072
  - Figure 362. TPIU Block Diagram1072
  - Table 228. Synchronous TRACE Pin Assignment1073
  - TPUI Formatter1074
  - Table 229. Flexible TRACE Pin Assignment1074
  - TPUI Frame Synchronization Packets1075
  - Transmission of the Synchronization Frame Packet1075
  - Synchronous Mode1075
  - Asynchronous Mode1076
  - TRACECLKIN Connection Inside the Stm32F10Xxx1076
  - TPIU Registers1077
  - Table 230. Important TPIU Registers1077
  - 31.17.10 Example of Configuration1078
- DBG Register Map1078
- Table 231. DBG Register Map and Reset Values1078
Revision History1079
- Table 96. Min/Max IWDG Timeout Period at 740 Khz (LSI)1080
- Table 83. Output Control Bits for Complementary Ocx and Ocxn Channels with1082
- Table 100. External Memory Address1086
- Table 113. Fsmc_Bcrx Bit Fields1086
- Table 122. Fsmc_Bcrx Bit Fields1086
- Table 130. 16-Bit NAND Flash1086
- Table 99. NOR/PSRAM Bank Selection1086
- Table 82. Timx Internal Trigger Connection1088
- Table 195. USART Interrupt Requests1089
- Table 204. OTG_FS Register Map and Reset Values1090
- Table 107. nor Flash/Psram Supported Memories and Transactions1091
- Table 108. Fsmc_Bcrx Bit Fields1091
- Table 131. 16-Bit PC Card1091
- Table 183. Audio-Frequency Precision Using Standard 25 Mhz and PLL31091
- Table 232. Document Revision History1091

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