ST STM32F101xx User Manual

RM0008 Revision history
Doc ID 13902 Rev 12 1091/1096
23-Apr-2010
11
continued
Updated Section 21: Flexible static memory controller (FSMC),
Updated Section 21.3: AHB interface on page 490
Updated Wrap support for NOR Flash/PSRAM on page 493
Added ASYNCWAIT, in Table 108: FSMC_BCRx bit fields on page 500
Added section WAIT management in asynchronous accesses on page 512
Updated Figure 200: Asynchronous wait during a write access on page 514
Updated Table 131: 16-bit PC Card on page 528
Added Section 21.6.7: PC Card/CompactFlash operations on page 532
Removed OTG_FS controller block diagram
Update Section 1.10.2: Peripheral Tx FIFOs
Added Section 1.12: FIFO RAM allocation
Updated Table 4: Core global control and status registers (CSRs)
Added method 1 and 2 in Section 26.3.3: I2C master mode
Updated note in POS bit description Section 26.6: I2C registers
Removed NPTXRWEN bit in Section 28: USB on-the-go full-speed (OTG_FS)
Updated formula for TRDT bit in Section 28: USB on-the-go full-speed (OTG_FS)
Removed BIM and TXFURM bits OTG_FS device IN endpoint common interrupt mask
register (OTG_FS_DIEPMSK)
Removed BOIM, OPEM, B2BSTUP bits in OTG_FS device OUT endpoint common
interrupt mask register (OTG_FS_DOEPMSK)
Updated Section 31.6.2: Boundary scan TAP on page 1056
12-Jan-2011 12
Added Section 1: Overview of the manual
Added FSMC boundary addresses to Table 3 on page 50
Added paragraph on HSI to Programming and erasing the Flash memory on page 59
Updated Table 11.12.12: ADC injected sequence register (ADC_JSQR) on page 240
Added “VREF shared with ADC in Section 12.1: DAC introduction on page 243
Updated example in Section 14.4.19: TIM1&TIM8 DMA control register (TIMx_DCR) on
page 343 and other timer sections.
Updated description of counter operation in Section 15.3.12: Encoder interface mode
Moved caution paragraph from RTC_PRLH to RTC PRLL in Section 18.4: RTC registers
Updated Table 107: NOR Flash/PSRAM supported memories and transactions on
page 497Changed data phase to data setup phase in FSMC WAIT management in
asynchronous accesses on page 512
Added note on shared SRAM for USB and CAN to Section 23.2: USB main features on
page 599
Updated LEC description in CAN error status register (CAN_ESR) on page 658
Updated CRCNEXT description in Section 25.3.6: CRC calculation on page 690
Corrected Figure 264: PCM standard waveforms (16-bit) on page 705
Updated Table 183: Audio-frequency precision using standard 25 MHz and PLL3
(connectivity line devices only) and Table 184: Audio-frequency precision using standard
14.7456 MHz and PLL3 (connectivity line devices only) on page 709
Updated BERR description in Section 26.6.6: Status register 1 (I2C_SR1) on page 752
Updated note 1 in Section 26.6.8: Clock control register (I2C_CCR) on page 756
Table 232. Document revision history (continued)
Date Revision Changes

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English