RM0008 Inter-integrated circuit (I
2
C) interface
Doc ID 13902 Rev 12 727/1096
–I
2
C busy flag
● Error flags:
– Arbitration lost condition for master mode
– Acknowledgement failure after address/ data transmission
– Detection of misplaced start or stop condition
– Overrun/Underrun if clock stretching is disabled
● 2 Interrupt vectors:
– 1 Interrupt for successful address/ data communication
– 1 Interrupt for error condition
● Optional clock stretching
● 1-byte buffer with DMA capability
● Configurable PEC (packet error checking) generation or verification:
– PEC value can be transmitted as last byte in Tx mode
– PEC error checking for last received byte
● SMBus 2.0 Compatibility:
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
– Hardware PEC generation/verification with ACK control
– Address Resolution Protocol (ARP) supported
● PMBus Compatibility
Note: Some of the above features may not be available in certain products. The user should refer
to the product data sheet, to identify the specific features supported by the I
2
C interface
implementation.
26.3 I
2
C functional description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I
2
C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz) or fast (up to 400 kHz) I
2
C bus.
26.3.1 Mode selection
The interface can operate in one of the four following modes:
● Slave transmitter
● Slave receiver
● Master transmitter
● Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master, after it generates a START condition and from master to slave, if an arbitration loss
or a Stop generation occurs, allowing multimaster capability.
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