RM0008 General-purpose timers (TIM2 to TIM5)
Doc ID 13902 Rev 12 369/1096
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.
PWM edge-aligned mode
Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Section :
Upcounting mode on page 351.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.
If the compare value is 0 then OCxREF is held at ‘0. Figure 130 shows some edge-aligned
PWM waveforms in an example where TIMx_ARR=8.
Figure 130. Edge-aligned PWM waveforms (ARR=8)
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting
mode on page 354
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 356.
Counter register
‘1
0
1234567801
‘0
OCxREF
CCxIF
OCxREF
CCxIF
OCxREF
CCxIF
OCxREF
CCxIF
CCRx=4
CCRx=8
CCRx>8
CCRx=0
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