Inter-integrated circuit (I
2
C) interface RM0008
734/1096 Doc ID 13902 Rev 12
Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from
the DR register to the SDA line via the internal shift register.
The master waits until the first data byte is written into I2C_DR (see Figure 272 Transfer
sequencing EV8_1).
When the acknowledge pulse is received:
● The TxE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bits are set.
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared by a read from I2C_SR1
followed by a write to I2C_DR, stretching SCL low.
Closing the communication
After the last byte is written to the DR register, the STOP bit is set by software to generate a
Stop condition (see Figure 272 Transfer sequencing EV8_2). The interface automatically
goes back to slave mode (M/SL bit cleared).
Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.
Figure 272. Transfer sequence diagram for master transmitter
7-bit master transmitter
10-bit master transmitter
Legend: S= Start, S
r
= Repeated Start, P= Stop, A= Acknowledge,
EVx= Event (with interrupt if ITEVFEN = 1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.
EV8_1: TxE=1, shift register empty, data register empty, write Data1 in DR.
EV8: TxE=1, shift register not empty, data register empty, cleared by writing DR register.
EV8_2: TxE=1, BTF = 1, Program Stop request. TxE
and BTF are cleared by hardware by the Stop condition
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.
S Address AData1A Data2A
.....
DataNA P
EV5 EV6 EV8_1 EV8 EV8 EV8 EV8_2
S Header A Address AData1A
.....
DataNA P
EV5 EV9 EV6 EV8_1 EV8 EV8 EV8_2
ai15881b
Notes: 1- The EV5, EV6, EV9, EV8_1 and EV8_2 events stretch SCL low until the end of the corresponding software sequence.
2- The EV8 software sequence must complete before the end of the current byte transfer. In case EV8 software
sequence can not be managed before the current byte end of transfer, it is recommended to use BTF instead
of TXE with the drawback of slowing the communication.
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