ST STM32F101xx User Manual

RM0008 Revision history
Doc ID 13902 Rev 12 1079/1096
32 Revision history
Table 232. Document revision history
Date Revision Changes
19-Oct-2007 1
Document reference number changed from UM0306 to RM008. The changes below were
made with reference to revision 1 of 01-Jun-2007 of UM0306.
EXTSEL[2:0] and JEXTSEL[2:0] removed from Table 65: ADC pins on page 208 and
V
REF+
range modified in Remarks column.
Notes added to Section 11.3.9 on page 212, Section 11.9.2 on page 220, Section 11.9.7
on page 223 and Section 11.9.9 on page 224.
SPI_CR2 corrected to SPI_CR1 in 1 clock and 1 bidirectional data wire (BIDIMODE=1) on
page 683.
f
CPU
frequency changed to f
PCLK
in Section 25.2: SPI and I2S main features on page 675.
Section 25.3.6: CRC calculation on page 690 and Section 25.3.9: SPI communication
using DMA (direct memory addressing) on page 694 modified.
Note added to bit 13 description changed in Section 25.5.1: SPI control register 1
(SPI_CR1) (not used in I2S mode) on page 716. Note for bit 4 modified in Section 25.5.3:
SPI status register (SPI_SR) on page 720.
On 64-pin packages and packages with less pins on page 66 modified.
Section 9.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 on page 169
updated.
Description of SRAM at address 0x4000 6000 modified in Figure 2: Memory map on
page 39 and Table 3: Register boundary addresses.
Note added to Section 23.2: USB main features on page 599 and Section 24.2: bxCAN
main features on page 630.
Figure 4: Power supply overview and On 100-pin and 144-pin packages modified.
Formula added to Bits 25:24 description in CAN bit timing register (CAN_BTR) on
page 659.
Section Figure 28.: DMA block diagram in high-density STM32L15xxx devices on
page 190 modified.
Example of configuration on page 1066 modified.
MODEx[1:0] bit definitions corrected in Section 9.2.2: Port configuration register high
(GPIOx_CRH) (x=A..G) on page 166.
Downcounting mode on page 287 modified.
Figure 81: Output stage of capture/compare channel (channel 4) on page 298 and
Figure 83: Output compare mode, toggle on OC1. modified. OCx output enable conditions
modified in Section 14.3.10: PWM mode on page 302.
Section 14.3.19: TIMx and external trigger synchronization on page 317 title changed.
CC1S, CC2S, CC3S and CC4S definitions modified for (1, 1) bit setting modified in
Section 14.4.7: TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) and
Section 14.4.8: TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2).
CC1S, CC2S, CC3S and CC4S definitions for (1, 1) bit setting modified in Section 15.4.7:
TIMx capture/compare mode register 1 (TIMx_CCMR1) and Section 15.4.8: TIMx
capture/compare mode register 2 (TIMx_CCMR2).
AFIO_EVCR pins modified in Table 60: AFIO register map and reset values on page 187.
Section 14.3.6: Input capture mode on page 298 modified.

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English