RM0008 Connectivity line devices: reset and clock control (RCC)
Doc ID 13902 Rev 12 149/1096
8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR)
Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Bit 24 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 23:2 Reserved, always read as 0.
Bit 1 LSIRDY: Internal low speed oscillator ready
Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock
cycles.
0: Internal RC 40 kHz oscillator not ready
1: Internal RC 40 kHz oscillator ready
Bit 0 LSION: Internal low speed oscillator enable
Set and cleared by software.
0: Internal RC 40 kHz oscillator OFF
1: Internal RC 40 kHz oscillator ON
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res.
ETHMAC
RST
Res.
OTGFS
RST
Reserved
rw rw
Bits 31:15 Reserved, always read as 0.
Bit 14 ETHMACRST Ethernet MAC reset
Set and cleared by software.
0: No effect
1: Reset ETHERNET MAC
Bit 13 Reserved, always read as 0.
Bit 12 OTGFSRST USB OTG FS reset
Set and cleared by software.
0: No effect
1: Reset USB OTG FS
Bits 11:0 Reserved, always read as 0.
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