Independent watchdog (IWDG) RM0008
478/1096 Doc ID 13902 Rev 12
19.3.2 Register access protection
Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you
must first write the code 0x5555 in the IWDG_KR register. A write access to this register
with a different value will break the sequence and register access will be protected again.
This implies that it is the case of the reload operation (writing 0xAAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
19.3.3 Debug mode
When the microcontroller enters debug mode (Cortex-M3 core halted), the IWDG counter
either continues to work normally or stops, depending on DBG_IWDG_STOP configuration
bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,
watchdog, bxCAN and I2C.
Figure 182. Independent watchdog block diagram
Note: The watchdog function is implemented in the V
DD
voltage domain that is still functional in
Stop and Standby modes.
The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy.
For more details refer to LSI clock on page 93.
IWDG RESET
prescaler
12-bit downcounter
IWDG_PR
Prescaler register
IWDG_RLR
Reload register
8-bit
LSI
IWDG_KR
Key register
1.8 V voltage domain
V
DD
voltage domain
IWDG_SR
Status register
12-bit reload value
(40 kHz)
Table 96. Min/max IWDG timeout period at 740 kHz (LSI)
(1)
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler divider PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 (or 7) 6.4 26214.4
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