Flexible static memory controller (FSMC) RM0008
512/1096 Doc ID 13902 Rev 12
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to advise that it's not yet ready to accept
or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data phase must be programmed so that WAIT can be detected 4 HCLK cycles before
the data sampling. The following cases must be considered:
Table 122. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-16 0x0000
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13-10 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 -
6 FACCEN 0x1
5-4 MWID As needed
3-2 MTYP 0x2 (NOR)
1 MUXEN 0x1
0 MBKEN 0x1
Table 123. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31-20 0x0000
19-16 BUSTURN
Duration of the last phase of the access (BUSTURN+1 HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles for
read accesses and DATAST+1 HCLK cycles for write accesses).
This value cannot be 0 (minimum is 1)
7-4 ADDHLD
Duration of the middle phase of the access (ADDHLD+1 HCLK
cycles).This value cannot be 0 (minimum is 1).
3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).
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