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ST STM32F101xx User Manual
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Flexible stati
c memory controller (FSMC)
RM0008
498/1096
Doc ID 13902 Rev 12
21.5.3
General timing rules
Signals synchr
onization
●
All controller output
signals change on the rising edge of the internal cloc
k (HCLK)
●
In synchronous write mode (PSRAM de
vices), the output data changes on the
fa
lling
edge of the memory clock (CLK)
497
499
Table of Contents
Default Chapter
2
Table of Contents
2
Overview of the Manual
40
Table 1. Sections Related to each Stm32F10Xxx Product
40
Table
40
Table 2. Sections Related to each Peripheral
43
Documentation Conventions
46
List of Abbreviations for Registers
46
Glossary
46
Peripheral Availability
46
Memory and Bus Architecture
47
System Architecture
47
Figure 1. System Architecture
47
Figure 2. System Architecture in Connectivity Line Devices
48
Memory Organization
49
Memory Map
50
Register Boundary Addresses
50
Embedded SRAM
53
Bit Banding
53
Embedded Flash Memory
54
Table
54
Flash Module Organization (Low-Density Devices)
54
Table 5. Flash Module Organization (Medium-Density Devices)
55
Table 6. Flash Module Organization (High-Density Devices)
56
Table 7. Flash Module Organization (Connectivity Line Devices)
57
Table 8. XL-Density Flash Module Organization
57
Boot Configuration
60
Table 9. Boot Modes
60
CRC Calculation Unit
62
CRC Introduction
62
CRC Main Features
62
Figure 3. CRC Calculation Unit Block Diagram
62
CRC Functional Description
63
CRC Registers
63
Data Register (CRC_DR)
63
Independent Data Register (CRC_IDR)
63
Control Register (CRC_CR)
64
CRC Register Map
64
Table 10. CRC Calculation Unit Register Map and Reset Values
64
Power Control (PWR)
65
Power Supplies
65
Independent A/D and D/A Converter Supply and Reference Voltage
66
Figure 4. Power Supply Overview
66
Battery Backup Domain
67
Voltage Regulator
68
Power Supply Supervisor
68
Power on Reset (Por)/Power down Reset (PDR)
68
Programmable Voltage Detector (PVD)
68
Figure 5. Power on Reset/Power down Reset Waveform
68
Figure 6. PVD Thresholds
69
Low-Power Modes
70
Slowing down System Clocks
70
Table 11. Low-Power Mode Summary
70
Peripheral Clock Gating
71
Sleep Mode
71
Stop Mode
72
Table 12. Sleep-Now
72
Table 13. Sleep-On-Exit
72
Standby Mode
73
Table 14. Stop Mode
73
Table 15. Standby Mode
74
Auto-Wakeup (AWU) from Low-Power Mode
75
Power Control Registers
75
Power Control Register (PWR_CR)
75
Power Control/Status Register (PWR_CSR)
77
PWR Register Map
78
Table 16. PWR Register Map and Reset Values
78
Backup Registers (BKP)
79
BKP Introduction
79
BKP Main Features
79
BKP Functional Description
80
Tamper Detection
80
RTC Calibration
80
BKP Registers
81
Backup Data Register X (Bkp_Drx) (X = 1
81
RTC Clock Calibration Register (BKP_RTCCR)
81
Backup Control Register (BKP_CR)
82
Backup Control/Status Register (BKP_CSR)
82
BKP Register Map
83
Table 17. BKP Register Map and Reset Values
83
Low-, Medium-, High- and XL-Density Reset and Clock Control (RCC)
87
Reset
87
System Reset
87
Power Reset
88
Backup Domain Reset
88
Figure 7. Simplified Diagram of the Reset Circuit
88
Clocks
89
Figure 8. Clock Tree
90
Figure 9. HSE/ LSE Clock Sources
91
HSE Clock
91
HSI Clock
92
Pll
92
LSE Clock
93
LSI Clock
93
Clock Security System (CSS)
94
RTC Clock
94
System Clock (SYSCLK) Selection
94
Clock-Out Capability
95
Watchdog Clock
95
RCC Registers
96
Clock Control Register (RCC_CR)
96
Clock Configuration Register (RCC_CFGR)
98
Clock Interrupt Register (RCC_CIR)
101
APB2 Peripheral Reset Register (RCC_APB2RSTR)
103
APB1 Peripheral Reset Register (RCC_APB1RSTR)
106
AHB Peripheral Clock Enable Register (RCC_AHBENR)
108
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
109
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
111
Backup Domain Control Register (RCC_BDCR)
115
Control/Status Register (RCC_CSR)
117
RCC Register Map
119
Table 18. RCC Register Map and Reset Values
119
Connectivity Line Devices: Reset and Clock Control (RCC)
120
Reset
120
System Reset
120
Power Reset
121
Figure 10. Simplified Diagram of the Reset Circuit
121
Backup Domain Reset
122
Clocks
122
Figure 11. Clock Tree
123
HSE Clock
124
Figure 12. HSE/ LSE Clock Sources
125
HSI Clock
125
LSE Clock
126
Plls
126
LSI Clock
127
System Clock (SYSCLK) Selection
127
Clock Security System (CSS)
128
RTC Clock
128
Watchdog Clock
128
Clock-Out Capability
129
RCC Registers
129
Clock Control Register (RCC_CR)
129
Clock Configuration Register (RCC_CFGR)
131
Clock Interrupt Register (RCC_CIR)
134
APB2 Peripheral Reset Register (RCC_APB2RSTR)
137
APB1 Peripheral Reset Register (RCC_APB1RSTR)
138
AHB Peripheral Clock Enable Register (RCC_AHBENR)
141
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
142
APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
144
Backup Domain Control Register (RCC_BDCR)
146
Control/Status Register (RCC_CSR)
148
AHB Peripheral Clock Reset Register (RCC_AHBRSTR)
149
Clock Configuration Register2 (RCC_CFGR2)
150
RCC Register Map
152
Table 19. RCC Register Map and Reset Values
152
General-Purpose and Alternate-Function I/Os (Gpios and Afios)
154
GPIO Functional Description
154
Figure 13. Basic Structure of a Standard I/O Port Bit
155
Figure 14. Basic Structure of a Five-Volt Tolerant I/O Port Bit
155
Atomic Bit Set or Reset
156
General-Purpose I/O (GPIO)
156
Table 20. Port Bit Configuration Table
156
Table 21. Output MODE Bits
156
Alternate Functions (AF)
157
External Interrupt/Wakeup Lines
157
GPIO Locking Mechanism
157
Software Remapping of I/O Alternate Functions
157
Figure 15. Input Floating/Pull Up/Pull down Configurations
158
Input Configuration
158
Output Configuration
158
Alternate Function Configuration
159
Figure 16. Output Configuration
159
Analog Configuration
160
Figure 17. Alternate Function Configuration
160
GPIO Configurations for Device Peripherals
161
Table 22. Advanced Timers TIM1/TIM8
161
Table 23. General-Purpose Timers TIM2/3/4/5
161
Usarts
161
Figure 18. High Impedance-Analog Configuration
161
Table 25. SPI
162
Table 26. I2S
162
Table 27. I2C
163
Table 28. Bxcan
163
Usb
163
Table 30. OTG_FS Pin Configuration
163
Sdio
164
Fsmc
164
Figure 19. ADC / DAC
164
Table 31. SDIO
164
Table 33. Other Ios
164
GPIO Registers
165
Port Configuration Register Low (Gpiox_Crl) (X=A..g
165
Port Configuration Register High (Gpiox_Crh) (X=A..g
166
Port Input Data Register (Gpiox_Idr) (X=A..g
166
Port Output Data Register (Gpiox_Odr) (X=A
167
Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A
167
Port Bit Reset Register (Gpiox_Brr) (X=A
168
Port Configuration Lock Register (Gpiox_Lckr) (X=A
168
Alternate Function I/O and Debug Configuration (AFIO)
169
Using OSC32_IN/OSC32_OUT Pins as GPIO Ports PC14/PC15
169
Using OSC_IN/OSC_OUT Pins as GPIO Ports PD0/PD1
169
CAN1 Alternate Function Remapping
170
CAN2 Alternate Function Remapping
170
JTAG/SWD Alternate Function Remapping
170
Table 34. CAN1 Alternate Function Remapping
170
Table 35. CAN2 Alternate Function Remapping
170
Table 36. Debug Interface Signals
170
ADC Alternate Function Remapping
171
Table 37. Debug Port Mapping
171
Table 38. ADC1 External Trigger Injected Conversion Alternate Function Remapping
171
Table 39. ADC1 External Trigger Regular Conversion Alternate Function Remapping
171
Table 40. ADC2 External Trigger Injected Conversion Alternate Function Remapping
171
Table 41. ADC2 External Trigger Regular Conversion Alternate Function Remapping
172
Table 42. TIM5 Alternate Function Remapping
172
Table 44. TIM3 Alternate Function Remapping
172
Timer Alternate Function Remapping
172
Table 46. TIM1 Alternate Function Remapping
173
Table 47. TIM9 Remapping
173
Table 48. TIM10 Remapping
173
Table 49. TIM11 Remapping
174
Table 50. TIM13 Remapping
174
Table 51. TIM14 Remapping
174
Table 52. USART3 Remapping
174
Table 53. USART2 Remapping
174
USART Alternate Function Remapping
174
Ethernet Alternate Function Remapping
175
I2C1 Alternate Function Remapping
175
SPI1 Alternate Function Remapping
175
SPI3/I2S3 Alternate Function Remapping
175
Table 54. USART1 Remapping
175
Table 55. I2C1 Remapping
175
Table 56. SPI1 Remapping
175
Table 57. SPI3/I2S3 Remapping
175
AFIO Registers
176
Table 58. ETH Remapping
176
Event Control Register (AFIO_EVCR)
177
AF Remap and Debug I/O Configuration Register (AFIO_MAPR)
178
External Interrupt Configuration Register 1 (AFIO_EXTICR1)
184
External Interrupt Configuration Register 2 (AFIO_EXTICR2)
184
External Interrupt Configuration Register 3 (AFIO_EXTICR3)
185
External Interrupt Configuration Register 4 (AFIO_EXTICR4)
185
AF Remap and Debug I/O Configuration Register2 (AFIO_MAPR2)
186
GPIO and AFIO Register Maps
187
Table 59. GPIO Register Map and Reset Values
187
Table 60. AFIO Register Map and Reset Values
187
Interrupts and Events
189
Nested Vectored Interrupt Controller (NVIC)
189
Systick Calibration Value Register
189
Interrupt and Exception Vectors
189
Table 61. Vector Table for Connectivity Line Devices
189
Table 62. Vector Table for XL-Density Devices
192
Table 63. Vector Table for Other Stm32F10Xxx Devices
195
External Interrupt/Event Controller (EXTI)
197
Main Features
197
Block Diagram
197
Wakeup Event Management
198
Functional Description
198
Figure 20. External Interrupt/Event Controller Block Diagram
198
External Interrupt/Event Line Mapping
199
Figure 21. External Interrupt/Event GPIO Mapping
200
EXTI Registers
201
Interrupt Mask Register (EXTI_IMR)
201
Event Mask Register (EXTI_EMR)
201
Rising Trigger Selection Register (EXTI_RTSR)
202
Falling Trigger Selection Register (EXTI_FTSR)
202
Software Interrupt Event Register (EXTI_SWIER)
203
Pending Register (EXTI_PR)
203
EXTI Register Map
204
Table 64. External Interrupt/Event Controller Register Map and Reset Values
204
Analog-To-Digital Converter (ADC)
205
ADC Introduction
205
ADC Main Features
206
ADC Functional Description
206
Figure 22. Single ADC Block Diagram
207
Table 65. ADC Pins
208
ADC Clock
209
ADC On-Off Control
209
Channel Selection
209
Single Conversion Mode
209
Continuous Conversion Mode
210
Figure 23. Timing Diagram
210
Timing Diagram
210
Analog Watchdog
211
Figure 24. Analog Watchdog Guarded Area
211
Scan Mode
211
Table 66. Analog Watchdog Channel Selection
211
Figure 25. Injected Conversion Latency
212
Injected Channel Management
212
Discontinuous Mode
213
Calibration
213
Data Alignment
214
Figure 26. Calibration Timing Diagram
214
Figure 27. Right Alignment of Data
214
Figure 28. Left Alignment of Data
214
Channel-By-Channel Programmable Sample Time
215
Conversion on External Trigger
215
Table 67. External Trigger for Regular Channels for ADC1 and ADC2
215
Table 68. External Trigger for Injected Channels for ADC1 and ADC2
216
Table 69. External Trigger for Regular Channels for ADC3
216
Table 70. External Trigger for Injected Channels for ADC3
216
DMA Request
217
Dual ADC Mode
218
Figure 29. Dual ADC Block Diagram
219
Figure 30. Injected Simultaneous Mode on 4 Channels
220
Injected Simultaneous Mode
220
Regular Simultaneous Mode
220
Fast Interleaved Mode
221
Figure 31. Regular Simultaneous Mode on 16 Channels
221
Figure 32. Fast Interleaved Mode on 1 Channel in Continuous Conversion Mode
221
Slow Interleaved Mode
221
Alternate Trigger Mode
222
Figure 33. Slow Interleaved Mode on 1 Channel
222
Figure 34. Alternate Trigger: Injected Channel Group of each ADC
222
Combined Regular Simultaneous + Alternate Trigger Mode
223
Combined Regular/Injected Simultaneous Mode
223
Figure 35. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Model
223
Independent Mode
223
Combined Injected Simultaneous + Interleaved
224
Figure 36. Alternate + Regular Simultaneous
224
Figure 37. Case of Trigger Occurring During Injected Conversion
224
Figure 38. Interleaved Single Channel with Injected Sequence CH11, CH12
224
Temperature Sensor
225
Figure 39. Temperature Sensor and VREFINT Channel Block Diagram
225
ADC Interrupts
226
Table 71. ADC Interrupts
226
ADC Registers
227
ADC Status Register (ADC_SR)
227
ADC Control Register 1 (ADC_CR1)
228
ADC Control Register 2 (ADC_CR2)
230
ADC Sample Time Register 1 (ADC_SMPR1)
234
ADC Sample Time Register 2 (ADC_SMPR2)
235
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
235
ADC Watchdog High Threshold Register (ADC_HTR)
236
ADC Watchdog Low Threshold Register (ADC_LTR)
236
ADC Regular Sequence Register 1 (ADC_SQR1)
237
ADC Regular Sequence Register 2 (ADC_SQR2)
238
ADC Regular Sequence Register 3 (ADC_SQR3)
239
ADC Injected Sequence Register (ADC_JSQR)
240
ADC Injected Data Register X (Adc_Jdrx) (X= 1
240
ADC Regular Data Register (ADC_DR)
241
11.12.15 ADC Register Map
241
Table 72. ADC Register Map and Reset Values
241
Digital-To-Analog Converter (DAC)
243
DAC Introduction
243
DAC Main Features
243
Table 73. DAC Pins
244
Figure 40. DAC Channel Block Diagram
244
DAC Functional Description
245
DAC Channel Enable
245
DAC Output Buffer Enable
245
DAC Data Format
245
DAC Conversion
246
Figure 41. Data Registers in Single DAC Channel Mode
246
Figure 42. Data Registers in Dual DAC Channel Mode
246
DAC Output Voltage
247
DAC Trigger Selection
247
Table 74. External Triggers
247
Figure 43. Timing Diagram for Conversion with Trigger Disabled TEN = 0
247
DMA Request
248
Noise Generation
248
Figure 44. DAC LFSR Register Calculation Algorithm
248
Triangle-Wave Generation
249
Figure 45. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
249
Figure 46. DAC Triangle Wave Generation
249
Dual DAC Channel Conversion
250
Independent Trigger Without Wave Generation
250
Figure 47. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
250
Independent Trigger with same LFSR Generation
251
Independent Trigger with Different LFSR Generation
251
Independent Trigger with same Triangle Generation
251
Independent Trigger with Different Triangle Generation
252
Simultaneous Software Start
252
Simultaneous Trigger Without Wave Generation
252
Simultaneous Trigger with same LFSR Generation
253
Simultaneous Trigger with Different LFSR Generation
253
Simultaneous Trigger with same Triangle Generation
253
Simultaneous Trigger with Different Triangle Generation
254
DAC Registers
254
DAC Control Register (DAC_CR)
254
DAC Software Trigger Register (DAC_SWTRIGR)
257
DAC Channel1 12-Bit Right-Aligned Data Holding Register
258
(Dac_Dhr12R1)
258
DAC Channel1 12-Bit Left Aligned Data Holding Register
258
(Dac_Dhr12L1)
258
DAC Channel1 8-Bit Right Aligned Data Holding Register
258
(Dac_Dhr8R1)
258
DAC Channel2 12-Bit Right Aligned Data Holding Register
259
(Dac_Dhr12R2)
259
DAC Channel2 12-Bit Left Aligned Data Holding Register
259
(Dac_Dhr12L2)
259
DAC Channel2 8-Bit Right-Aligned Data Holding Register
259
(Dac_Dhr8R2)
259
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
260
DUAL DAC 12-Bit Left Aligned Data Holding Register
260
(Dac_Dhr12Ld)
260
DUAL DAC 8-Bit Right Aligned Data Holding Register
261
(Dac_Dhr8Rd)
261
DAC Channel1 Data Output Register (DAC_DOR1)
261
DAC Channel2 Data Output Register (DAC_DOR2)
261
DAC Register Map
262
Table 75. DAC Register Map
262
DMA Controller (DMA)
263
DMA Introduction
263
DMA Main Features
263
Figure 48. DMA Block Diagram in Connectivity Line Devices
264
DMA Functional Description
265
DMA Transactions
265
Figure 49. DMA Block Diagram in Low-, Medium- High- and XL-Density Devices
265
Arbiter
266
DMA Channels
266
Programmable Data Width, Data Alignment and Endians
268
Table 76. Programmable Data Width & Endian Behavior (When Bits PINC = MINC = 1)
268
Error Management
269
Interrupts
269
Table 77. DMA Interrupt Requests
269
DMA Request Mapping
270
Figure 50. DMA1 Request Mapping
270
Table 78. Summary of DMA1 Requests for each Channel
271
Table 79. Summary of DMA2 Requests for each Channel
272
Figure 51. DMA2 Request Mapping
272
DMA Registers
273
DMA Interrupt Status Register (DMA_ISR)
273
DMA Interrupt Flag Clear Register (DMA
274
DMA Channel X Configuration Register (Dma_Ccrx) (X = 1
275
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
276
DMA Channel X Peripheral Address Register (Dma_Cparx) (X = 1
277
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
277
DMA Register Map
278
Table 80. DMA Register Map and Reset Values
278
Advanced-Control Timers (TIM1&TIM8)
280
TIM1&TIM8 Introduction
280
TIM1&TIM8 Main Features
281
Figure 52. Advanced-Control Timer Block Diagram
282
TIM1&TIM8 Functional Description
283
Time-Base Unit
283
Counter Modes
284
Figure 53. Counter Timing Diagram with Prescaler Division Change from 1 to 2
284
Figure 54. Counter Timing Diagram with Prescaler Division Change from 1 to 4
284
Figure 55. Counter Timing Diagram, Internal Clock Divided by 1
285
Figure 56. Counter Timing Diagram, Internal Clock Divided by 2
285
Figure 57. Counter Timing Diagram, Internal Clock Divided by 4
286
Figure 58. Counter Timing Diagram, Internal Clock Divided by N
286
Figure 59. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
286
Figure 60. Counter Timing Diagram, Update Event When ARPE=1
287
Figure 61. Counter Timing Diagram, Internal Clock Divided by 1
288
Figure 62. Counter Timing Diagram, Internal Clock Divided by 2
288
Figure 63. Counter Timing Diagram, Internal Clock Divided by 4
288
Figure 64. Counter Timing Diagram, Internal Clock Divided by N
289
Figure 65. Counter Timing Diagram, Update Event When Repetition Counter
289
Figure 66. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
290
Figure 67. Counter Timing Diagram, Internal Clock Divided by 2
291
Figure 68. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
291
Figure 69. Counter Timing Diagram, Internal Clock Divided by N
291
Repetition Counter
292
Figure 70. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
292
Figure 71. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
292
Figure 72. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
293
Clock Selection
294
Figure 73. Control Circuit in Normal Mode, Internal Clock Divided by 1
294
Figure 74. TI2 External Clock Connection Example
294
Figure 75. Control Circuit in External Clock Mode 1
295
Figure 76. External Trigger Input Block
295
Capture/Compare Channels
296
Figure 77. Control Circuit in External Clock Mode 2
296
Figure 78. Capture/Compare Channel (Example: Channel 1 Input Stage)
297
Figure 79. Capture/Compare Channel 1 Main Circuit
297
Input Capture Mode
298
Figure 80. Output Stage of Capture/Compare Channel (Channel 1 to 3)
298
Figure 81. Output Stage of Capture/Compare Channel (Channel 4)
298
PWM Input Mode
299
Forced Output Mode
300
Figure 82. PWM Input Mode Timing
300
Output Compare Mode
301
PWM Mode
302
Figure 83. Output Compare Mode, Toggle on OC1
302
Figure 84. Edge-Aligned PWM Waveforms (ARR=8)
303
Figure 85. Center-Aligned PWM Waveforms (ARR=8)
304
Complementary Outputs and Dead-Time Insertion
305
Figure 86. Complementary Output with Dead-Time Insertion
305
Figure 87. Dead-Time Waveforms with Delay Greater than the Negative Pulse
305
Using the Break Function
306
Figure 88. Dead-Time Waveforms with Delay Greater than the Positive Pulse
306
Figure 89. Output Behavior in Response to a Break
308
Clearing the Ocxref Signal on an External Event
309
Figure 90. Clearing Timx Ocxref
309
6-Step PWM Generation
310
Figure 91. 6-Step Generation, COM Example (OSSR=1)
310
One-Pulse Mode
311
Figure 92. Example of One Pulse Mode
311
Encoder Interface Mode
312
Table 81. Counting Direction Versus Encoder Signals
313
Figure 93. Example of Counter Operation in Encoder Interface Mode
314
Figure 94. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
314
Timer Input XOR Function
315
Interfacing with Hall Sensors
315
Figure 95. Example of Hall Sensor Interface
316
Timx and External Trigger Synchronization
317
Figure 96. Control Circuit in Reset Mode
317
Figure 97. Control Circuit in Gated Mode
318
Figure 98. Control Circuit in Trigger Mode
319
Timer Synchronization
320
Debug Mode
320
Figure 99. Control Circuit in External Clock Mode 2 + Trigger Mode
320
TIM1&TIM8 Registers
321
TIM1&TIM8 Control Register 1 (Timx_Cr1)
321
TIM1&TIM8 Control Register 2 (Timx_Cr2)
322
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
324
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
326
TIM1&TIM8 Status Register (Timx_Sr)
328
TIM1&TIM8 Event Generation Register (Timx_Egr)
329
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
331
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
334
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
335
TIM1&TIM8 Counter (Timx_Cnt)
338
TIM1&TIM8 Prescaler (Timx_Psc)
338
TIM1&TIM8 Auto-Reload Register (Timx_Arr)
338
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
339
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)
339
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
340
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)
340
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
341
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)
341
TIM1&TIM8 DMA Control Register (Timx_Dcr)
343
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
344
TIM1&TIM8 Register Map
344
Table 84. TIM1&TIM8 Register Map and Reset Values
344
General-Purpose Timers (TIM2 to TIM5)
347
TIM2 to TIM5 Introduction
347
Timx Main Features
348
Timx Functional Description
349
Time-Base Unit
349
Figure 100. General-Purpose Timer Block Diagram
349
Figure 101. Counter Timing Diagram with Prescaler Division Change from 1 to 2
350
Counter Modes
351
Figure 102. Counter Timing Diagram with Prescaler Division Change from 1 to 4
351
Figure 103. Counter Timing Diagram, Internal Clock Divided by 1
352
Figure 104. Counter Timing Diagram, Internal Clock Divided by 2
352
Figure 105. Counter Timing Diagram, Internal Clock Divided by 4
352
Figure 106. Counter Timing Diagram, Internal Clock Divided by N
353
Figure 107. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
353
Figure 108. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
354
Figure 109. Counter Timing Diagram, Internal Clock Divided by 1
355
Figure 110. Counter Timing Diagram, Internal Clock Divided by 2
355
Figure 111. Counter Timing Diagram, Internal Clock Divided by 4
355
Figure 112. Counter Timing Diagram, Internal Clock Divided by N
356
Figure 113. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
356
Figure 114. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
357
Figure 115. Counter Timing Diagram, Internal Clock Divided by 2
358
Figure 116. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
358
Figure 117. Counter Timing Diagram, Internal Clock Divided by N
358
Figure 118. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
359
Figure 119. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
359
Clock Selection
360
Figure 120. Control Circuit in Normal Mode, Internal Clock Divided by 1
360
Figure 121. TI2 External Clock Connection Example
361
Figure 122. Control Circuit in External Clock Mode 1
361
Figure 123. External Trigger Input Block
362
Figure 124. Control Circuit in External Clock Mode 2
362
Capture/Compare Channels
363
Figure 125. Capture/Compare Channel (Example: Channel 1 Input Stage)
363
Figure 126. Capture/Compare Channel 1 Main Circuit
363
Figure 127. Output Stage of Capture/Compare Channel (Channel 1)
364
Input Capture Mode
365
PWM Input Mode
366
Figure 128. PWM Input Mode Timing
366
Forced Output Mode
367
Output Compare Mode
367
PWM Mode
368
Figure 129. Output Compare Mode, Toggle on OC1
368
Figure 130. Edge-Aligned PWM Waveforms (ARR=8)
369
Figure 131. Center-Aligned PWM Waveforms (ARR=8)
370
One-Pulse Mode
371
Figure 132. Example of One-Pulse Mode
371
Clearing the Ocxref Signal on an External Event
372
Encoder Interface Mode
373
Figure 133. Clearing Timx Ocxref
373
Table 85. Counting Direction Versus Encoder Signals
374
Figure 134. Example of Counter Operation in Encoder Interface Mode
374
Timer Input XOR Function
375
Timers and External Trigger Synchronization
375
Figure 135. Example of Encoder Interface Mode with IC1FP1 Polarity Inverted
375
Figure 136. Control Circuit in Reset Mode
376
Figure 137. Control Circuit in Gated Mode
377
Figure 138. Control Circuit in Trigger Mode
377
Timer Synchronization
378
Figure 139. Control Circuit in External Clock Mode 2 + Trigger Mode
378
Figure 140. Master/Slave Timer Example
379
Figure 141. Gating Timer 2 with OC1REF of Timer 1
380
Figure 142. Gating Timer 2 with Enable of Timer 1
381
Figure 143. Triggering Timer 2 with Update of Timer 1
381
Figure 144. Triggering Timer 2 with Enable of Timer 1
382
Debug Mode
383
Figure 145. Triggering Timer 1 and 2 with Timer 1 TI1 Input
383
Timx2 to TIM5 Registers
384
Timx Control Register 1 (Timx_Cr1)
384
Timx Control Register 2 (Timx_Cr2)
386
Timx Slave Mode Control Register (Timx_Smcr)
387
Table 86. Timx Internal Trigger Connection
388
Timx Dma/Interrupt Enable Register (Timx_Dier)
390
Timx Status Register (Timx_Sr)
391
Timx Event Generation Register (Timx_Egr)
393
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
394
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
397
Timx Capture/Compare Enable Register (Timx_Ccer)
398
Timx Counter (Timx_Cnt)
399
Timx Prescaler (Timx_Psc)
399
Table 87. Output Control Bit for Standard Ocx Channels
399
Timx Auto-Reload Register (Timx_Arr)
400
Timx Capture/Compare Register 1 (Timx_Ccr1)
401
Timx Capture/Compare Register 2 (Timx_Ccr2)
401
Timx Capture/Compare Register 3 (Timx_Ccr3)
402
Timx Capture/Compare Register 4 (Timx_Ccr4)
402
Timx DMA Control Register (Timx_Dcr)
403
Timx DMA Address for Full Transfer (Timx_Dmar)
403
Timx Register Map
405
Table 88. Timx Register Map and Reset Values
405
General-Purpose Timers (TIM9 to TIM14)
408
TIM9 to TIM14 Introduction
408
TIM9 to TIM14 Main Features
409
TIM9/TIM12 Main Features
409
Figure 146. General-Purpose Timer Block Diagram (TIM9 and TIM12)
409
TIM10/TIM11 and TIM13/TIM14 Main Features
410
Figure 147. General-Purpose Timer Block Diagram (TIM10/11/13/14)
410
TIM9 to TIM14 Functional Description
411
Time-Base Unit
411
Counter Modes
412
Figure 148. Counter Timing Diagram with Prescaler Division Change from 1 to 2
412
Figure 149. Counter Timing Diagram with Prescaler Division Change from 1 to 4
412
Figure 150. Counter Timing Diagram, Internal Clock Divided by 1
413
Figure 151. Counter Timing Diagram, Internal Clock Divided by 2
413
Figure 152. Counter Timing Diagram, Internal Clock Divided by 4
414
Figure 153. Counter Timing Diagram, Internal Clock Divided by N
414
Clock Selection
415
Figure 156. Control Circuit in Normal Mode, Internal Clock Divided by 1
416
Figure 157. TI2 External Clock Connection Example
416
Capture/Compare Channels
417
Figure 158. Control Circuit in External Clock Mode 1
417
Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage)
417
Input Capture Mode
418
Figure 160. Capture/Compare Channel 1 Main Circuit
418
Figure 161. Output Stage of Capture/Compare Channel (Channel 1)
418
PWM Input Mode (Only for TIM9/12)
419
Forced Output Mode
420
Figure 162. PWM Input Mode Timing
420
Output Compare Mode
421
PWM Mode
422
Figure 163. Output Compare Mode, Toggle on OC1
422
Figure 164. Edge-Aligned PWM Waveforms (ARR=8)
423
One-Pulse Mode (Only for TIM9/12)
424
Figure 165. Example of One Pulse Mode
424
TIM9/12 External Trigger Synchronization
426
Figure 166. Control Circuit in Reset Mode
426
Figure 167. Control Circuit in Gated Mode
427
Timer Synchronization (TIM9/12)
428
Debug Mode
428
Figure 168. Control Circuit in Trigger Mode
428
TIM9 and TIM12 Registers
429
TIM9/12 Control Register 1 (Timx_Cr1)
429
TIM9/12 Control Register 2 (Timx_Cr2)
430
TIM9/12 Slave Mode Control Register (Timx_Smcr)
431
Table 89. Timx Internal Trigger Connection
431
TIM9/12 Interrupt Enable Register (Timx_Dier)
432
TIM9/12 Status Register (Timx_Sr)
433
TIM9/12 Event Generation Register (Timx_Egr)
434
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
435
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
438
TIM9/12 Counter (Timx_Cnt)
439
TIM9/12 Prescaler (Timx_Psc)
439
TIM9/12 Auto-Reload Register (Timx_Arr)
439
Table 90. Output Control Bit for Standard Ocx Channels
439
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
440
TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)
440
TIM9/12 Register Map
441
Table 91. TIM9/12 Register Map and Reset Values
441
TIM10/11/13/14 Registers
442
TIM10/11/13/14 Control Register 1 (Timx_Cr1)
442
TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)
443
TIM10/11/13/14 Status Register (Timx_Sr)
443
TIM10/11/13/14 Event Generation Register (Timx_Egr)
444
TIM10/11/13/14 Capture/Compare Mode Register 1
445
(Timx_Ccmr1)
445
TIM10/11/13/14 Capture/Compare Enable Register
448
(Timx_Ccer)
448
Table 92. Output Control Bit for Standard Ocx Channels
448
TIM10/11/13/14 Counter (Timx_Cnt)
449
TIM10/11/13/14 Prescaler (Timx_Psc)
449
TIM10/11/13/14 Auto-Reload Register (Timx_Arr)
449
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
450
TIM10/11/13/14 Register Map
450
Table 93. TIM10/11/13/14 Register Map and Reset Values
450
Basic Timers (TIM6&TIM7)
452
TIM6&TIM7 Introduction
452
TIM6&TIM7 Main Features
452
TIM6&TIM7 Functional Description
453
Time-Base Unit
453
Figure 169. Basic Timer Block Diagram
453
Figure 170. Counter Timing Diagram with Prescaler Division Change from 1 to 2
454
Figure 171. Counter Timing Diagram with Prescaler Division Change from 1 to 4
454
Counting Mode
455
Figure 172. Counter Timing Diagram, Internal Clock Divided by 1
455
Figure 173. Counter Timing Diagram, Internal Clock Divided by 2
456
Figure 174. Counter Timing Diagram, Internal Clock Divided by 4
456
Figure 175. Counter Timing Diagram, Internal Clock Divided by N
456
Clock Source
457
Debug Mode
458
TIM6&TIM7 Registers
458
TIM6&TIM7 Control Register 1 (Timx_Cr1)
458
Figure 178. Control Circuit in Normal Mode, Internal Clock Divided by 1
458
TIM6&TIM7 Control Register 2 (Timx_Cr2)
460
TIM6&TIM7 Dma/Interrupt Enable Register (Timx_Dier)
460
TIM6&TIM7 Status Register (Timx_Sr)
461
TIM6&TIM7 Event Generation Register (Timx_Egr)
461
TIM6&TIM7 Counter (Timx_Cnt)
461
TIM6&TIM7 Prescaler (Timx_Psc)
462
TIM6&TIM7 Auto-Reload Register (Timx_Arr)
462
TIM6&TIM7 Register Map
463
Table 94. TIM6&TIM7 Register Map and Reset Values
463
Real-Time Clock (RTC)
464
RTC Introduction
464
RTC Main Features
465
RTC Functional Description
466
Overview
466
Figure 179. RTC Simplified Block Diagram
466
Resetting RTC Registers
467
Reading RTC Registers
467
Configuring RTC Registers
467
RTC Flag Assertion
468
Figure 180. RTC Second and Alarm Waveform Example with PR=0003, ALARM=00004
468
Figure 181. RTC Overflow Waveform Example with PR=0003
468
RTC Registers
469
RTC Control Register High (RTC_CRH)
469
RTC Control Register Low (RTC_CRL)
470
RTC Prescaler Load Register (RTC_PRLH / RTC_PRLL)
471
RTC Prescaler Divider Register (RTC_DIVH / RTC_DIVL)
472
RTC Counter Register (RTC_CNTH / RTC_CNTL)
473
RTC Alarm Register High (RTC_ALRH / RTC_ALRL)
474
RTC Register Map
475
Table 95. RTC Register Map and Reset Values
475
Independent Watchdog (IWDG)
476
IWDG Introduction
476
IWDG Main Features
476
IWDG Functional Description
476
Hardware Watchdog
477
Register Access Protection
478
Debug Mode
478
Figure 182. Independent Watchdog Block Diagram
478
IWDG Registers
479
Key Register (IWDG_KR)
479
Prescaler Register (IWDG_PR)
479
Reload Register (IWDG_RLR)
480
Status Register (IWDG_SR)
480
IWDG Register Map
481
Table 97. IWDG Register Map and Reset Values
481
Window Watchdog (WWDG)
482
WWDG Introduction
482
WWDG Main Features
482
WWDG Functional Description
482
Figure 183. Watchdog Block Diagram
483
How to Program the Watchdog Timeout
484
Debug Mode
484
Figure 184. Window Watchdog Timing Diagram
484
WWDG Registers
485
Control Register (WWDG_CR)
485
Configuration Register (WWDG_CFR)
486
Status Register (WWDG_SR)
486
WWDG Register Map
487
Table 98. WWDG Register Map and Reset Values
487
Flexible Static Memory Controller (FSMC)
488
FSMC Main Features
488
Block Diagram
489
AHB Interface
490
Figure 185. FSMC Block Diagram
490
Supported Memories and Transactions
491
External Device Address Mapping
492
NOR/PSRAM Address Mapping
492
Figure 186. FSMC Memory Banks
492
NAND/PC Card Address Mapping
493
Table 101. Memory Mapping and Timing Registers
493
Table 102. NAND Bank Selections
493
NOR Flash/Psram Controller
494
Table 103. Programmable NOR/PSRAM Access Parameters
494
External Memory Interface Signals
495
Table 104. Nonmuxed I/O nor Flash
495
Table 105. Muxed I/O nor Flash
495
Supported Memories and Transactions
496
Table 106. Non Muxed I/Os PSRAM/SRAM
496
General Timing Rules
498
Figure 187. Mode1 Read Accesses
499
NOR Flash/Psram Controller Asynchronous Transactions
499
Figure 188. Mode1 Write Accesses
500
Figure 189. Modea Read Accesses
501
Table 109. Fsmc_Btrx Bit Fields
501
Figure 190. Modea Write Accesses
502
Table 110. Fsmc_Bcrx Bit Fields
502
Table 111. Fsmc_Btrx Bit Fields
503
Table 112. Fsmc_Bwtrx Bit Fields
503
Figure 191. Mode2/B Read Accesses
504
Figure 192. Mode2 Write Accesses
504
Figure 193. Modeb Write Accesses
505
Table 114. Fsmc_Btrx Bit Fields
506
Table 115. Fsmc_Bwtrx Bit Fields
506
Figure 194. Modec Read Accesses
507
Figure 195. Modec Write Accesses
507
Table 116. Fsmc_Bcrx Bit Fields
508
Table 117. Fsmc_Btrx Bit Fields
508
Table 118. Fsmc_Bwtrx Bit Fields
508
Figure 196. Moded Read Accesses
509
Table 119. Fsmc_Bcrx Bit Fields
510
Table 120. Fsmc_Btrx Bit Fields
510
Table 121. Fsmc_Bwtrx Bit Fields
510
Figure 197. Muxed Read Accesses
511
Figure 198. Muxed Write Accesses
511
Table 123. Fsmc_Btrx Bit Fields
512
Figure 199. Asynchronous Wait During a Read Access
513
Figure 200. Asynchronous Wait During a Write Access
514
Synchronous Burst Transactions
515
Figure 201. Wait Configurations
516
Figure 202. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)
517
Table 124. Fsmc_Bcrx Bit Fields
517
Table 125. Fsmc_Btrx Bit Fields
518
Figure 203. Synchronous Multiplexed Write Mode - PSRAM (CRAM)
519
Table 126. Fsmc_Bcrx Bit Fields
520
Table 127. Fsmc_Btrx Bit Fields
520
NOR/PSRAM Controller Registers
521
NAND Flash/Pc Card Controller
526
External Memory Interface Signals
527
Table 128. Programmable NAND/PC Card Access Parameters
527
Table 129. 8-Bit NAND Flash
527
NAND Flash / PC Card Supported Memories and Transactions
529
Timing Diagrams for NAND and PC Card
529
Table 132. Supported Memories and Transactions
529
NAND Flash Operations
530
Figure 204. NAND/PC Card Controller Timing for Common Memory Access
530
NAND Flash Pre-Wait Functionality
531
Figure 205. Access to Non 'CE Don't Care' NAND-Flash
531
Error Correction Code Computation ECC (NAND Flash)
532
PC Card/Compactflash Operations
532
Table 133. 16-Bit PC-Card Signals and Access Type
533
NAND Flash/Pc Card Controller Registers
535
Table 134. ECC Result Relevant Bits
540
FSMC Register Map
541
Table 135. FSMC Register Map
541
Secure Digital Input/Output Interface (SDIO)
543
SDIO Main Features
543
SDIO Bus Topology
544
Figure 206. SDIO "No Response" and "No Data" Operations
544
Figure 207. SDIO (Multiple) Block Read Operation
544
Figure 208. SDIO (Multiple) Block Write Operation
545
Figure 209. SDIO Sequential Read Operation
545
Figure 210. SDIO Sequential Write Operation
545
SDIO Functional Description
546
Figure 211. SDIO Block Diagram
546
Figure 212. SDIO Adapter
547
SDIO Adapter
547
Table 136. SDIO I/O Definitions
547
Figure 213. Control Unit
548
Figure 214. SDIO Adapter Command Path
549
Figure 215. Command Path State Machine (CPSM)
550
Figure 216. SDIO Command Transfer
551
Table 137. Command Format
551
Table 138. Short Response Format
552
Table 139. Long Response Format
552
Table 140. Command Path Status Flags
552
Figure 217. Data Path
553
Figure 218. Data Path State Machine (DPSM)
554
Table 141. Data Token Format
555
Table 142. Transmit FIFO Status Flags
556
SDIO AHB Interface
557
Table 143. Receive FIFO Status Flags
557
Card Functional Description
558
Card Identification Mode
558
Card Reset
558
Operating Voltage Range Validation
558
Card Identification Process
559
Block Write
560
Block Read
560
Stream Access, Stream Write and Stream Read (Multimediacard Only)
561
Erase: Group Erase and Sector Erase
562
Wide Bus Selection or Deselection
563
Protection Management
563
Card Status Register
566
Table 144. Card Status
567
SD Status Register
569
Table 145. SD Status
569
Table 146. Speed Class Code Field
571
Table 147. Performance Move Field
571
Table 148. AU_SIZE Field
572
Table 149. Maximum AU Size
572
Table 150. Erase Size Field
572
Table 151. Erase Timeout Field
572
SD I/O Mode
573
Table 152. Erase Offset Field
573
Commands and Responses
574
Table 153. Block-Oriented Write Commands
575
Table 154. Block-Oriented Write Protection Commands
576
Table 155. Erase Commands
576
Table 156. I/O Mode Commands
576
Response Formats
577
Table 157. Lock Card
577
Table 158. Application-Specific Commands
577
R1 (Normal Response Command)
578
R1B
578
R2 (CID, CSD Register)
578
R3 (OCR Register)
578
Table 159. R1 Response
578
Table 160. R2 Response
578
R4 (Fast I/O)
579
R4B
579
Table 161. R3 Response
579
Table 162. R4 Response
579
Table 163. R4B Response
579
R5 (Interrupt Request)
580
Table 164. R5 Response
580
Table 165. R6 Response
580
SDIO I/O Card-Specific Operations
581
SDIO I/O Read Wait Operation by SDIO_D2 Signalling
581
SDIO Read Wait Operation by Stopping SDIO_CK
581
SDIO Suspend/Resume Operation
582
SDIO Interrupts
582
CE-ATA Specific Operations
582
Command Completion Signal Disable
582
Command Completion Signal Enable
582
CE-ATA Interrupt
583
Aborting CMD61
583
HW Flow Control
583
SDIO Registers
583
SDIO Power Control Register (SDIO_POWER)
584
SDI Clock Control Register (SDIO_CLKCR)
584
SDIO Argument Register (SDIO_ARG)
585
SDIO Command Register (SDIO_CMD)
586
SDIO Command Response Register (SDIO_RESPCMD)
587
SDIO Response 1
587
Table 166. Response Type and Sdio_Respx Registers
587
SDIO Data Timer Register (SDIO_DTIMER)
588
SDIO Data Length Register (SDIO_DLEN)
588
SDIO Data Control Register (SDIO_DCTRL)
589
SDIO Data Counter Register (SDIO_DCOUNT)
590
SDIO Status Register (SDIO_STA)
591
SDIO Interrupt Clear Register (SDIO_ICR)
592
SDIO Mask Register (SDIO_MASK)
594
SDIO FIFO Counter Register (SDIO_FIFOCNT)
596
SDIO Data FIFO Register (SDIO_FIFO)
597
SDIO Register Map
597
Table 167. SDIO Register Map
597
Universal Serial Bus Full-Speed Device Interface (USB)
599
USB Introduction
599
USB Main Features
599
USB Functional Description
599
Figure 219. USB Peripheral Block Diagram
600
Description of USB Blocks
601
Programming Considerations
602
Generic USB Device Programming
602
System and Power-On Reset
603
Figure 220. Packet Buffer Areas with Examples of Buffer Description Table Locations
604
Double-Buffered Endpoints
608
Table 168. Double-Buffering Buffer Flag Definition
609
Table 169. Bulk Double-Buffering Memory Buffers Usage
609
Isochronous Transfers
610
Suspend/Resume Events
611
Table 170. Isochronous Memory Buffers Usage
611
Table 171. Resume Event Detection
612
USB Registers
613
Common Registers
614
Endpoint-Specific Registers
621
Table 172. Reception Status Encoding
624
Table 173. Endpoint Type Encoding
624
Table 174. Endpoint Kind Meaning
624
Buffer Descriptor Table
625
Table 175. Transmission Status Encoding
625
USB Register Map
628
Table 176. Definition of Allocated Buffer Memory
628
Table 177. USB Register Map and Reset Values
628
Controller Area Network (Bxcan)
630
Bxcan Introduction
630
Bxcan Main Features
630
Bxcan General Description
631
Figure 221. CAN Network Topology
631
Acceptance Filters
632
CAN 2.0B Active Core
632
Control, Status and Configuration Registers
632
Tx Mailboxes
632
Bxcan Operating Modes
633
Figure 222. Dual CAN Block Diagram (Connectivity Devices)
633
Initialization Mode
634
Normal Mode
634
Sleep Mode (Low Power)
634
Test Mode
635
Silent Mode
635
Figure 223. Bxcan Operating Modes
635
Loop Back Mode
636
Loop Back Combined with Silent Mode
636
Figure 224. Bxcan in Silent Mode
636
Figure 225. Bxcan in Loop Back Mode
636
Stm32F10Xxx in Debug Mode
637
Bxcan Functional Description
637
Transmission Handling
637
Figure 226. Bxcan in Combined Mode
637
Figure 227. Transmit Mailbox States
638
Time Triggered Communication Mode
639
Reception Handling
639
Figure 228. Receive FIFO States
639
Identifier Filtering
640
Figure 229. Filter Bank Scale Configuration - Register Organization
642
Figure 230. Example of Filter Numbering
643
Message Storage
644
Figure 231. Filtering Mechanism - Example
644
Table 178. Transmit Mailbox Mapping
645
Table 179. Receive Mailbox Mapping
645
Figure 232. CAN Error State Diagram
645
Error Management
646
Bit Timing
646
Figure 233. Bit Timing
647
Bxcan Interrupts
648
Figure 234. CAN Frames
648
Figure 235. Event Flags and Interrupt Generation
649
CAN Registers
650
Register Access Protection
650
CAN Control and Status Registers
650
CAN Mailbox Registers
660
CAN Filter Registers
667
Bxcan Register Map
671
Table 180. Bxcan Register Map and Reset Values
671
Serial Peripheral Interface (SPI)
674
SPI Introduction
674
SPI and I 2 S Main Features
675
SPI Features
675
I 2 S Features
676
SPI Functional Description
677
General Description
677
Figure 236. SPI Block Diagram
677
Figure 237. Single Master/ Single Slave Application
678
Figure 238. Hardware/Software Slave Select Management
679
Configuring the SPI in Slave Mode
680
Figure 239. Data Clock Timing Diagram
680
Configuring the SPI in Master Mode
682
Configuring the SPI for Simplex Communication
683
Data Transmission and Reception Procedures
683
Figure 240. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode (BIDIMODE=0 and RXONLY=0)
686
Figure 241. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode (BIDIMODE=0, RXONLY=0) in the
686
Figure 242. TXE/BSY Behavior in Master Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the
687
Figure 243. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in the Case of
688
Figure 244. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1) in the Case of
689
CRC Calculation
690
Figure 245. TXE/BSY Behavior When Transmitting (BIDIRMODE=0 and RXONLY=0) in the Case of
690
Status Flags
692
Disabling the SPI
693
SPI Communication Using DMA (Direct Memory Addressing)
694
Figure 246. Transmission Using DMA
694
Error Flags
695
Figure 247. Reception Using DMA
695
SPI Interrupts
696
Table 181. SPI Interrupt Requests
696
S Functional Description
697
S General Description
697
Figure 248. I
697
Supported Audio Protocols
698
Figure 249. I 2 S Phillips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
699
Figure 250. I 2 S Phillips Standard Waveforms (24-Bit Frame with CPOL = 0)
699
Figure 251. Transmitting 0X8Eaa33
700
Figure 252. Receiving 0X8Eaa33
700
Figure 253. I 2 S Phillips Standard (16-Bit Extended to 32-Bit Packet Frame with CPOL = 0)
700
Figure 254. Example
701
Figure 255. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
701
Figure 256. MSB Justified 24-Bit Frame Length with CPOL = 0
702
Figure 257. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
702
Figure 258. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
702
Figure 259. LSB Justified 24-Bit Frame Length with CPOL = 0
703
Figure 260. Operations Required to Transmit 0X3478Ae
703
Figure 261. Operations Required to Receive 0X3478Ae
703
Figure 262. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
704
Figure 263. Example
704
Clock Generator
705
Figure 264. PCM Standard Waveforms (16-Bit)
705
Figure 265. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
705
Figure 266. Audio Sampling Frequency Definition
706
Figure 267. I
706
Table 182. Audio-Frequency Precision Using Standard 8 Mhz HSE
707
(Connectivity Line Devices Only)
708
Table 184. Audio-Frequency Precision Using Standard 14.7456 Mhz and PLL3
709
I 2 S Master Mode
710
I 2 S Slave Mode
711
Status Flags
713
Error Flags
714
DMA Features
715
I 2 S Interrupts
715
Table 185. I S Interrupt Requests
715
SPI and I 2 S Registers
716
SPI Control Register 1 (SPI_CR1)
716
Mode)
716
SPI Control Register 2 (SPI_CR2)
719
SPI Status Register (SPI_SR)
720
SPI Data Register (SPI_DR)
721
SPI CRC Polynomial Register (SPI_CRCPR)
721
Mode)
721
SPI RX CRC Register (SPI_RXCRCR)
722
Mode)
722
SPI TX CRC Register (SPI_TXCRCR)
722
SPI_I 2 S Configuration Register (SPI_I2SCFGR)
723
SPI_I 2 S Prescaler Register (SPI_I2SPR)
724
SPI Register Map
725
Table 186. SPI Register Map and Reset Values
725
Inter-Integrated Circuit (I 2 C) Interface
726
I 2 C Introduction
726
I 2 C Main Features
726
I 2 C Functional Description
727
Mode Selection
727
Figure 268. I2C Bus Protocol
728
I2C Slave Mode
729
Figure 269. I2C Block Diagram
729
Figure 270. Transfer Sequence Diagram for Slave Transmitter
730
I2C Master Mode
731
Figure 271. Transfer Sequence Diagram for Slave Receiver
731
Figure 272. Transfer Sequence Diagram for Master Transmitter
734
Figure 273. Method 1: Transfer Sequence Diagram for Master Receiver
736
Figure 274. Method 2: Transfer Sequence Diagram for Master Receiver When N>2
737
Figure 275. Method 2: Transfer Sequence Diagram for Master Receiver When N=2
738
Error Conditions
739
Figure 276. Method 2: Transfer Sequence Diagram for Master Receiver When N=1
739
SDA/SCL Line Control
740
Smbus
741
Table 187. Smbus Vs. I2C
741
DMA Requests
743
Packet Error Checking
745
I 2 C Interrupts
745
Table 188. I2C Interrupt Requests
745
Figure 277. I2C Interrupt Mapping Diagram
746
I 2 C Debug Mode
747
I 2 C Registers
747
Control Register 1 (I2C_CR1)
747
Control Register 2 (I2C_CR2)
749
Own Address Register 1 (I2C_OAR1)
750
Own Address Register 2 (I2C_OAR2)
751
Data Register (I2C_DR)
751
Status Register 1 (I2C_SR1)
752
Status Register 2 (I2C_SR2)
755
Clock Control Register (I2C_CCR)
756
TRISE Register (I2C_TRISE)
757
I2C Register Map
758
Table 189. I2C Register Map and Reset Values
758
Universal Synchronous Asynchronous Receiver Transmitter (USART)
759
USART Introduction
759
USART Main Features
760
USART Functional Description
761
USART Block Diagramusart Character Description
763
Figure 278. Word Length Programming
764
Transmitter
765
Figure 279. Configurable Stop Bits
766
Figure 280. TC/TXE Behavior When Transmitting
767
Receiver
768
Figure 281. Start Bit Detection
768
Figure 282. Data Sampling for Noise Detection
770
Table 190. Noise Detection from Sampled Data
771
Fractional Baud Rate Generation
772
Table 191. Error Calculation for Programmed Baud Rates
773
USART Receiver's Tolerance to Clock Deviation
774
Multiprocessor Communication
774
Table 192. USART Receiver's Tolerance When Div_Fraction Is 0
774
Table 193. USART Receiver's Tolerance When Div_Fraction Is Different from 0
774
Figure 283. Mute Mode Using Idle Line Detection
775
Parity Control
776
Table 194. Frame Formats
776
Figure 284. Mute Mode Using Address Mark Detection
776
LIN (Local Interconnection Network) Mode
777
Figure 285. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
778
USART Synchronous Mode
779
Figure 286. Break Detection in LIN Mode Vs. Framing Error Detection
779
Figure 287. USART Example of Synchronous Transmission
780
Figure 288. USART Data Clock Timing Diagram (M=0)
780
Single-Wire Half-Duplex Communication
781
Figure 289. USART Data Clock Timing Diagram (M=1)
781
Figure 290. RX Data Setup/Hold Time
781
Smartcard
782
Figure 291. ISO 7816-3 Asynchronous Protocol
782
Irda SIR ENDEC Block
784
Figure 292. Parity Error Detection Using the 1.5 Stop Bits
784
Continuous Communication Using DMA
786
Figure 293. Irda SIR ENDEC- Block Diagram
786
Figure 294. Irda Data Modulation (3/16) -Normal Mode
786
Figure 295. Transmission Using DMA
787
Figure 296. Reception Using DMA
788
Hardware Flow Control
789
Figure 297. Hardware Flow Control between Two Usarts
789
Figure 298. RTS Flow Control
789
USART Interrupts
790
Figure 299. CTS Flow Control
790
USART Mode Configuration
791
USART Registers
791
Figure 300. USART Interrupt Mapping Diagram
791
Table 196. USART Mode Configuration
791
Status Register (USART_SR)
792
Baud Rate Register (USART_BRR)
794
Data Register (USART_DR)
794
Control Register 1 (USART_CR1)
795
Control Register 2 (USART_CR2)
797
Control Register 3 (USART_CR3)
798
Guard Time and Prescaler Register (USART_GTPR)
800
Table 197. USART Register Map and Reset Values
801
USART Register Map
801
USB On-The-Go Full-Speed (OTG_FS)
802
OTG_FS Introduction
802
OTG_FS Main Features
803
General Features
803
Host-Mode Features
804
Peripheral-Mode Features
804
OTG_FS Functional Description
805
OTG Full-Speed Core
805
Full-Speed OTG PHY
805
Figure 301. Block Diagram
805
OTG Dual Role Device (DRD)
806
Figure 302. OTG A-B Device Connection
806
HNP Dual Role Device
807
ID Line Detection
807
SRP Dual Role Device
807
USB Peripheral
808
SRP-Capable Peripheral
808
Figure 303. USB Peripheral-Only Connection
808
Peripheral States
809
Peripheral Endpoints
810
USB Host
812
SRP-Capable Host
813
USB Host States
813
Figure 304. USB Host-Only Connection
813
Host Channels
814
Host Scheduler
816
SOF Trigger
817
Host Sofs
817
Peripheral Sofs
817
Figure 305. SOF Connectivity
817
Power Options
818
Dynamic Update of the OTG_FS_HFIR Register
819
USB Data Fifos
819
Figure 306. Updating OTG_FS_HFIR Dynamically
819
Peripheral FIFO Architecture
820
Peripheral Rx FIFO
820
Figure 307. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
820
Peripheral Tx Fifos
821
Host FIFO Architecture
821
Host Rx FIFO
821
Figure 308. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
821
Host Tx Fifos
822
FIFO RAM Allocation
822
Device Mode
822
Host Mode
823
USB System Performance
823
OTG_FS Interrupts
824
Figure 309. Interrupt Hierarchy
825
OTG_FS Control and Status Registers
826
CSR Memory Map
827
Table 198. Core Global Control and Status Registers (Csrs)
827
Figure 310. CSR Memory Map
827
Table 199. Host-Mode Control and Status Registers (Csrs)
828
Table 200. Device-Mode Control and Status Registers
829
OTG_FS Global Registers
831
Table 201. Data FIFO (DFIFO) Access Register Map
831
Table 202. Power and Clock Gating Control and Status Registers
831
Host-Mode Registers
852
Device-Mode Registers
863
Table 203. Minimum Duration for Soft Disconnect
865
OTG_FS Power and Clock Gating Control Register
885
(Otg_Fs_Pcgcctl)
885
OTG_FS Register Map
886
OTG_FS Programming Model
892
Core Initialization
892
Host Initialization
894
Device Initialization
894
Host Programming Model
895
Figure 311. Transmit FIFO Write Task
896
Figure 312. Receive FIFO Read Task
897
Figure 313. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions
899
Figure 314. Bulk/Control in Transactions
902
Figure 315. Normal Interrupt OUT/IN Transactions
904
Figure 316. Normal Isochronous OUT/IN Transactions
909
Device Programming Model
912
Operational Model
914
Figure 317. Receive FIFO Packet Read
915
Figure 318. Processing a SETUP Packet
917
Figure 319. Bulk out Transaction
923
Worst Case Response Time
931
OTG Programming Model
932
Figure 320. TRDT Max Timing Case
932
Figure 321. A-Device SRP
933
Figure 322. B-Device SRP
934
Figure 323. A-Device HNP
935
Figure 324. B-Device HNP
936
Ethernet (ETH): Media Access Control (MAC) with DMA Controller
938
Ethernet Introduction
938
Ethernet Main Features
938
MAC Core Features
939
DMA Features
940
PTP Features
940
Ethernet Pins
941
Table 205. Ethernet Pin Configuration
941
Ethernet Functional Description: SMI, MII and RMII
942
Station Management Interface: SMI
942
Figure 325. ETH Block Diagram
942
Table 206. Management Frame Format
943
Figure 326. SMI Interface Signals
943
Figure 327. MDIO Timing and Frame Structure - Write Cycle
944
Media-Independent Interface: MII
945
Table 207. Clock Range
945
Figure 328. MDIO Timing and Frame Structure - Read Cycle
945
Figure 329. Media Independent Interface Signals
946
Table 208. TX Interface Signal Encoding
947
Table 209. RX Interface Signal Encoding
947
Reduced Media-Independent Interface: RMII
948
Figure 330. MII Clock Sources
948
Figure 331. Reduced Media-Independent Interface Signals
948
MII/RMII Selection
949
Figure 332. RMII Clock Sources
949
Figure 333. Clock Scheme
949
Ethernet Functional Description: MAC 802.3
950
MAC 802.3 Frame Format
950
Figure 334. Address Field Format
951
Figure 335. MAC Frame Format
953
Figure 336. Tagged MAC Frame Format
953
MAC Frame Transmission
954
Figure 337. Transmission Bit Order
959
Figure 338. Transmission with no Collision
960
Figure 339. Transmission with Collision
960
MAC Frame Reception
961
Figure 340. Frame Transmission in MMI and RMII Modes
961
Table 210. Frame Statuses
963
Figure 341. Receive Bit Order
965
Figure 342. Reception with no Error
965
Figure 343. Reception with Errors
965
MAC Interrupts
966
MAC Filtering
966
Figure 344. Reception with False Carrier Indication
966
Figure 345. MAC Core Interrupt Masking Scheme
966
Table 211. Destination Address Filtering Table
968
MAC Loopback Mode
969
MAC Management Counters: MMC
969
Table 212. Source Address Filtering Table
969
Power Management: PMT
970
Figure 346. Wakeup Frame Filter Register
971
Precision Time Protocol (IEEE1588 PTP)
973
Figure 347. Networked Time Synchronization
974
Figure 348. System Time Update Using the Fine Correction Method
976
Figure 349. PTP Trigger Output to TIM2 ITR1 Connection
978
Ethernet Functional Description: DMA Controller Operation
979
Figure 350. PPS Output
979
Figure 351. Descriptor Ring and Chain Structure
980
Host Bus Burst Access
980
Initialization of a Transfer Using DMA
980
Buffer Size Calculations
981
Host Data Buffer Alignment
981
DMA Arbiter
982
Error Response to DMA
982
Tx DMA Configuration
982
Figure 352. Txdma Operation in Default Mode
984
Figure 353. Txdma Operation in OSF Mode
986
Figure 354. Transmit Descriptor
987
Rx DMA Configuration
991
Figure 355. Receive DMA Operation
993
Figure 356. Rx DMA Descriptor Structure
995
Table 213. Receive Descriptor 0
997
DMA Interrupts
1000
Ethernet Interrupts
1001
Figure 357. Interrupt Scheme
1001
Ethernet Register Descriptions
1002
MAC Register Description
1002
Figure 358. Ethernet MAC Remote Wakeup Frame Filter Register (ETH_MACRWUFFR)
1011
MMC Register Description
1019
IEEE 1588 Time Stamp Registers
1024
DMA Register Description
1028
Ethernet Register Maps
1042
Table 214. Ethernet Register Map and Reset Values
1042
Device Electronic Signature
1045
Memory Size Registers
1045
Flash Size Register
1045
Unique Device ID Register (96 Bits)
1046
Debug Support (DBG)
1048
Overview
1048
Cortex-M3-Level Debug Support
1049
Figure 359. Block Diagram of Stm32F10Xxx-Level and
1049
Reference ARM Documentation
1050
SWJ Debug Port (Serial Wire and JTAG)
1050
Mechanism to Select the JTAG-DP or the SW-DP
1050
Figure 360. SWJ Debug Port
1050
Pinout and Debug Port Pins
1051
SWJ Debug Port Pins
1052
Flexible SWJ-DP Pin Assignment
1052
Table 215. SWJ Debug Port Pins
1052
Internal Pull-Up and Pull-Down on JTAG Pins
1053
Table 216. Flexible SWJ-DP Pin Assignment
1053
Using Serial Wire and Releasing the Unused Debug Pins as Gpios
1054
Stm32F10Xxx JTAG TAP Connection
1054
ID Codes and Locking Mechanism
1055
MCU Device ID Code
1055
Figure 361. JTAG TAP Connections
1055
Boundary Scan TAP
1056
Cortex-M3 TAP
1057
Cortex-M3 JEDEC-106 ID Code
1057
JTAG Debug Port
1057
Table 217. JTAG Debug Port Data Registers
1057
Table 218. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1058
SW Debug Port
1059
SW Protocol Introduction
1059
SW Protocol Sequence
1059
Table 219. Packet Request (8-Bits)
1059
SW-DP State Machine (Reset, Idle States, ID Code)
1060
DP and AP Read/Write Accesses
1060
Table 220. ACK Response (3 Bits)
1060
Table 221. DATA Transfer (33 Bits)
1060
SW-DP Registers
1061
SW-AP Registers
1061
Table 222. SW-DP Registers
1061
AHB-AP (AHB Access Port) - Valid for both JTAG-DP and SW-DP
1062
Table 223. Cortex-M3 AHB-AP Registers
1062
Capability of the Debugger Host to Connect under System Reset
1063
Core Debug
1063
Table 224. Core Debug Registers
1063
DWT (Data Watchpoint Trigger)
1064
FPB (Flash Patch Breakpoint)
1064
ITM (Instrumentation Trace Macrocell)
1065
General Description
1065
Time Stamp Packets, Synchronization and Overflow Packets
1065
Table 225. Main ITM Registers
1066
ETM (Embedded Trace Macrocell)
1067
General Description
1067
Signal Protocol, Packet Types
1067
Main ETM Registers
1067
Table 226. Main ETM Registers
1067
Configuration Example
1068
MCU Debug Component (DBGMCU)
1068
Debug Support for Low-Power Modes
1068
Debug Support for Timers, Watchdog, Bxcan and I C
1068
Debug MCU Configuration Register
1069
TPIU (Trace Port Interface Unit)
1072
Introduction
1072
TRACE Pin Assignment
1072
Table 227. Asynchronous TRACE Pin Assignment
1072
Figure 362. TPIU Block Diagram
1072
Table 228. Synchronous TRACE Pin Assignment
1073
TPUI Formatter
1074
Table 229. Flexible TRACE Pin Assignment
1074
TPUI Frame Synchronization Packets
1075
Transmission of the Synchronization Frame Packet
1075
Synchronous Mode
1075
Asynchronous Mode
1076
TRACECLKIN Connection Inside the Stm32F10Xxx
1076
TPIU Registers
1077
Table 230. Important TPIU Registers
1077
31.17.10 Example of Configuration
1078
DBG Register Map
1078
Table 231. DBG Register Map and Reset Values
1078
Revision History
1079
Table 96. Min/Max IWDG Timeout Period at 740 Khz (LSI)
1080
Table 83. Output Control Bits for Complementary Ocx and Ocxn Channels with
1082
Table 100. External Memory Address
1086
Table 113. Fsmc_Bcrx Bit Fields
1086
Table 122. Fsmc_Bcrx Bit Fields
1086
Table 130. 16-Bit NAND Flash
1086
Table 99. NOR/PSRAM Bank Selection
1086
Table 82. Timx Internal Trigger Connection
1088
Table 195. USART Interrupt Requests
1089
Table 204. OTG_FS Register Map and Reset Values
1090
Table 107. nor Flash/Psram Supported Memories and Transactions
1091
Table 108. Fsmc_Bcrx Bit Fields
1091
Table 131. 16-Bit PC Card
1091
Table 183. Audio-Frequency Precision Using Standard 25 Mhz and PLL3
1091
Table 232. Document Revision History
1091
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ST STM32F101xx Specifications
General
Brand
ST
Model
STM32F101xx
Category
Microcontrollers
Language
English
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