Inter-integrated circuit (I
2
C) interface RM0008
750/1096 Doc ID 13902 Rev 12
26.6.3 Own address register 1 (I2C_OAR1)
Address offset: 0x08
Reset value: 0x0000
Bit 9 ITEVTEN: Event interrupt enable
0: Event interrupt disabled
1: Event interrupt enabled
This interrupt is generated when:
–SB = 1 (Master)
–ADDR = 1 (Master/Slave)
–ADD10= 1 (Master)
–STOPF = 1 (Slave)
–BTF = 1 with no TxE or RxNE event
–TxE event to 1 if ITBUFEN = 1
–RxNE event to 1if ITBUFEN = 1
Bit 8 ITERREN: Error interrupt enable
0: Error interrupt disabled
1: Error interrupt enabled
This interrupt is generated when:
–BERR = 1
–ARLO = 1
–AF = 1
–OVR = 1
– PECERR = 1
–TIMEOUT = 1
–SMBALERT = 1
Bits 7:6 Reserved, forced by hardware to 0.
Bits 5:0 FREQ[5:0]: Peripheral clock frequency
The peripheral clock frequency must be configured using the input APB clock frequency (I2C
peripheral connected to APB). The minimum allowed frequency is 2 MHz, the maximum
frequency is limited by the maximum APB frequency (36 MHz) and an intrinsic limitation of
46 MHz.
0b000000: Not allowed
0b000001: Not allowed
0b000010: 2 MHz
...
0b100100: 36 MHz
Higher than 0b100100: Not allowed
15141312111098 7 654321 0
ADD
MODE
Reserved
ADD[9:8] ADD[7:1] ADD0
rw rw rw rw rw rw rw rw rw rw rw
Bit 15 ADDMODE Addressing mode (slave mode)
0: 7-bit slave address (10-bit address not acknowledged)
1: 10-bit slave address (7-bit address not acknowledged)
Bit 14 Should always be kept at 1 by software.
To Next Page
Loading...
Need help?
General
