RM0008 Flexible static memory controller (FSMC)
Doc ID 13902 Rev 12 519/1096
Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM)
1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Addr[15:0] data
addr[25:16]
Memory transaction = burst of 2 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
Hi-Z
NADV
NWAIT
(WAITCFG = 0)
A/D[15:0]
1 clock
cycle
1 clock
cycle
(DATALAT + 2)
inserted wait state
ai14731d
CLK cycles
data
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