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RM0008 Ethernet (ETH): media access control (MAC) with DMA controller

Doc ID 13902 Rev 12 1013/1096

Ethernet MAC interrupt status register (ETH_MACSR)

Address offset: 0x0038

Reset value: 0x0000 0000

The ETH_MACSR register contents identify the events in the MAC that can generate an

interrupt.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

TSTS

Reserved

MMCTS MMCRS MMCS PMTS

Reserved

rc_r r r r r

Bits 15:10 Reserved

Bit 9 TSTS: Time stamp trigger status

This bit is set high when the system time value equals or exceeds the value specified in the

Target time high and low registers. This bit is cleared when this register is read.

Bits 8:7 Reserved

Bit 6 MMCTS: MMC transmit status

This bit is set high whenever an interrupt is generated in the ETH_MMCTIR Register. This bit is

cleared when all the bits in this interrupt register (ETH_MMCTIR) are cleared.

Bit 5 MMCRS: MMC receive status

This bit is set high whenever an interrupt is generated in the ETH_MMCRIR register. This bit is

cleared when all the bits in this interrupt register (ETH_MMCRIR) are cleared.

Bit 4 MMCS: MMC status

This bit is set high whenever any of bits 6:5 is set high. It is cleared only when both bits are low.

Bit 3 PMTS: PMT status

This bit is set whenever a Magic packet or Wake-on-LAN frame is received in Power-down

mode (See bits 5 and 6 in the ETH_MACPMTCSR register Ethernet MAC PMT control and

status register (ETH_MACPMTCSR) on page 1012). This bit is cleared when both bits[6:5], of

this last register, are cleared due to a read operation to the ETH_MACPMTCSR register.

Bits 2:0 Reserved

ST STM32F101xx User Manual

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