RM0008 Revision history
Doc ID 13902 Rev 12 1085/1096
26-Sep-2008 6
This reference manual also applies to low-density STM32F101xx, STM32F102xx and
STM32F103xx devices, and to medium-density STM32F102xx devices. In all sections,
definitions of low-density and medium-density devices updated.
Section 2.3: Peripheral availability on page 46 added.
Section 3.3.3: Embedded Flash memory on page 54 updated. Section 5.1.2: Battery
backup domain on page 67 modified. Reset value of Port input data register (GPIOx_IDR)
(x=A..G) on page 166 modified. Note added in Section 9.4: AFIO registers on page 176.
Note removed from bits 18:0 description in Section 10.3.6: Pending register (EXTI_PR) on
page 203.
Section 14.2: TIM1&TIM8 main features on page 281 and Section 15.2: TIMx main
features on page 348 updated. In Section 15.3.15: Timer synchronization on page 378,
TS=000.
FSMC_CLK signal direction corrected in Figure 185: FSMC block diagram on page 490.
“Feedback clock” paragraph removed from Section 21.5.3: General timing rules on
page 498.
In Section 21.5.6: NOR/PSRAM controller registers on page 521: reset value modified,
WAITEN bit default value after reset is 1, bits [5:6] definition modified, , FACCEN default
value after reset specified. NWE signal behavior corrected in Figure 203: Synchronous
multiplexed write mode - PSRAM (CRAM) on page 519. The FSMC interface does not
support COSMO RAM and OneNAND devices, and it does not support the asynchronous
wait feature. SRAM and ROM 32 memory data size removed from Table 107: NOR
Flash/PSRAM supported memories and transactions on page 497.
Data latency versus NOR Flash latency on page 515 modified. Bits 19:16 bits are reserved
in SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) on page 525.
Section 21.6.3: Timing diagrams for NAND and PC Card on page 529 modified.Definition
of PWID bits modified in Section 21.6.8: NAND Flash/PC Card controller registers on
page 535. Section 21.6.6: Error correction code computation ECC (NAND Flash) on
page 532 modified.
Interrupt Mapper definition modified in Section 23.3.1: Description of USB blocks on
page 601. USB register and memory base addresses modified in Section 23.5: USB
registers on page 613.
Section 26.3.8: Packet error checking on page 745 modified.
Section : Start bit detection on page 768 added. PE bit description specified in Status
register (USART_SR) on page 792.
“RAM size register” section removed from Section 30: Device electronic signature on
page 1045. Bit definitions updated in FIFO status and interrupt register 2..4
(FSMC_SR2..4) on page 536.
Small text changes.
Table 232. Document revision history (continued)
Date Revision Changes
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