ST STM32F101xx User Manual

Revision history RM0008
1084/1096 Doc ID 13902 Rev 12
22-May-2008
continued
4
continued
Figure 234: CAN frames on page 648 modified. Bits 31:21 and bits 20:3 modified in CAN
TX mailbox identifier register (CAN_TIxR) (x=0..2) on page 661. Bits 31:21 and bits 20:3
modified in CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1) on
page 664.
Section 26.3.7: DMA requests on page 743 modified. DMAEN bit 11 description modified
in Section 26.6.2: Control register 2 (I2C_CR2) on page 749.
Clock phase and clock polarity on page 679 modified. Transmit sequence on page 681
modified. Receive sequence on page 682 added. Reception sequence on page 713
modified. Underrun flag (UDR) on page 714 modified.
I
2
S feature added (see Section 25: Serial peripheral interface (SPI) on page 674).
In Section 31: Debug support (DBG) on page 1048:
– DBGMCU_IDCODE on page 1055 and DBGMCU_CR on page 1069 updated
– TMC TAP changed to boundary scan TAP
– Address onto which DBGMCU_CR is mapped modified in Section 31.16.3: Debug MCU
configuration register on page 1069.
Section 30: Device electronic signature on page 1045 added.
REV_ID(15:0) definition modified in Section 31.6.1: MCU device ID code on page 1055.
28-Jul-2008 5
Developed polynomial form updated in Section 4.2: CRC main features on page 62.
Figure 4: Power supply overview on page 66 modified.
Section 5.1.2: Battery backup domain on page 67 modified.
Section 7.2.5: LSI clock on page 93 specified.
Section 9.1.4: Alternate functions (AF) on page 157 clarified.
Note added to Table 45: TIM2 alternate function remapping on page 173.
Bits are write-only in Section 13.4.2: DMA interrupt flag clear register (DMA_IFCR) on
page 274.
Register name modified in Section 11.3.1: ADC on-off control on page 209.
Recommended sampling time given in Section 11.10: Temperature sensor on page 225.
Bit attributes modified in Section 11.12.1: ADC status register (ADC_SR) on page 227.
Note modified for bits 23:0 in Section 11.12.4: ADC sample time register 1 (ADC_SMPR1)
on page 234.
Note added in Section 12.2: DAC main features on page 243.
Formula updated in Section 12.3.5: DAC output voltage on page 247.
DBL[4:0] description modified in Section 14.3.19: TIMx and external trigger
synchronization on page 317.
Figure 82 on page 300 and Figure 128 on page 366 modified.
Section 25.5.3: SPI status register (SPI_SR) on page 720 modified.
Closing the communication on page 735 updated.
Notes added to Section 26.6.8: Clock control register (I2C_CCR) on page 756. TCK
replaced by T
PCLK1
in Section 26.6.8 and Section 26.6.9.
OVR changed to ORE in Figure 300: USART interrupt mapping diagram on page 791.
Section 27.6.1: Status register (USART_SR) on page 792 updated.
Slave select (NSS) pin management on page 678 clarified.
Small text changes.
Table 232. Document revision history (continued)
Date Revision Changes

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English