ST STM32F101xx User Manual

RM0008 Revision history
Doc ID 13902 Rev 12 1087/1096
11-Feb-2009 8
Reset value corrected in Section 4.4.1: Data register (CRC_DR).
Section 11.10: Temperature sensor modified. Reset value corrected in Section 11.12.7:
ADC watchdog high threshold register (ADC_HTR).
Section 12.3.9: Triangle-wave generation and Figure 46: DAC triangle wave generation
updated.
Section 24.6: STM32F10xxx in Debug mode added. Bit 16 updated in CAN master control
register (CAN_MCR) on page 650.
Note added to Section 25.3.6: CRC calculation.
Changes concerning the I
2
C peripheral (Inter-integrated circuit (I2C) interface):
–In Slave transmitter on page 730: text changes and Figure 270: Transfer sequence
diagram for slave transmitter modified.
–In Slave receiver on page 731: text changes and Figure 271: Transfer sequence diagram
for slave receiver modified.
– Master transmitter on page 734 and Master receiver on page 735 clarified.
–In Closing the communication on page 734: text changes and Figure 272: Transfer
sequence diagram for master transmitter modified.
– Figure 273: Method 1: transfer sequence diagram for master receiver modified.
– Overrun/underrun error (OVR) on page 740 clarified.
– Section 26.3.7: DMA requests and Section 26.3.8: Packet error checking updated.
–In Section 26.6.1: Control register 1 (I2C_CR1): note modified under STOP bit and notes
modified under POS bit.
– Receiver mode modified in DR bit description in Section 26.6.5: Data register (I2C_DR).
– Note added to TxE and RxNE bit descriptions in Section 26.6.6: Status register 1
(I2C_SR1).
Changes in FSMC section:
– Data setup and Address hold min values corrected in Table 103: Programmable
NOR/PSRAM access parameters.
– Memory wait min value corrected in Table 128: Programmable NAND/PC Card access
parameters.
– Bit descriptions modified in SRAM/NOR-Flash chip-select timing registers 1..4
(FSMC_BTR1..4) on page 523.
– DATAST and ADDHLD are reserved when equal to 0x0000 in SRAM/NOR-Flash chip-
select timing registers 1..4 (FSMC_BTR1..4) on page 523 and SRAM/NOR-Flash write
timing registers 1..4 (FSMC_BWTR1..4) on page 525.
– Bit descriptions modified in Common memory space timing register 2..4
(FSMC_PMEM2..4)
– ATTHOLDx and ATTWAITx bit descriptions modified in Attribute memory space timing
registers 2..4 (FSMC_PATT2..4)
– IOHOLDx bit description modified in I/O space timing register 4 (FSMC_PIO4)
Table 232. Document revision history (continued)
Date Revision Changes

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English