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RM0008 Ethernet (ETH): media access control (MAC) with DMA controller

Doc ID 13902 Rev 12 1027/1096

Ethernet PTP time stamp low update register (ETH_PTPTSLUR)

Address offset: 0x0714

Reset value: 0x0000 0000

This register contains the least significant (lower) 32 bits of the time to be written to, added

to, or subtracted from the System Time value.

Ethernet PTP time stamp addend register (ETH_PTPTSAR)

Address offset: 0x0718

Reset value: 0x0000 0000

This register is used by the software to readjust the clock frequency linearly to match the

master clock frequency. This register value is used only when the system time is configured

for Fine update mode (TSFCU bit in ETH_PTPTSCR). This register content is added to a

32-bit accumulator in every clock cycle and the system time is updated whenever the

accumulator overflows.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TSUPNS

TSUSS

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Bit 31 TSUPNS: Time stamp update positive or negative sign

This bit indicates positive or negative time value. When set, the bit indicates that time

representation is negative. When cleared, it indicates that time representation is positive.

When TSSTI is set (system time initialization) this bit should be zero. If this bit is set when

TSSTU is set, the value in the Time stamp update registers is subtracted from the system

time. Otherwise it is added to the system time.

Bits 30:0 TSUSS: Time stamp update subseconds

The value in this field indicates the subsecond time to be initialized or added to the system

time. This value has an accuracy of 0.46 ns (in other words, a value of 0x0000_0001 is

0.46 ns).

313029282726252423222120191817161514131211109876543210

TSA

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Bits 31:0 TSA: Time stamp addend

This register indicates the 32-bit time value to be added to the Accumulator register to achieve

time synchronization.

ST STM32F101xx User Manual

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