Connectivity line devices: reset and clock control (RCC) RM0008
130/1096 Doc ID 13902 Rev 12
Bit 27 PLL2RDY: PLL2 clock ready flag
Set by hardware to indicate that the PLL2 is locked.
0: PLL2 unlocked
1: PLL2 locked
Bit 26 PLL2ON: PLL2 enable
Set and cleared by software to enable PLL2.
Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if
the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is
used as system clock).
0: PLL2 OFF
1: PLL2 ON
Bit 25 PLLRDY: PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock. Software
must disable the USB OTG FS clock before clearing this bit.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, always read as 0.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable clock detector.
0: Clock detector OFF
1: Clock detector ON if external 3-25 MHz oscillator is ready.
Bit 18 HSEBYP: External high-speed clock bypass
Set and cleared by software for bypassing the oscillator with an external clock. This bit can
be written only if the external 3-25 MHz oscillator is disabled.
0: external 3-25 MHz oscillator not bypassed
1: external 3-25 MHz oscillator bypassed with external clock
Bit 17 HSERDY: External high-speed clock ready flag
Set by hardware to indicate that the external 3-25 MHz oscillator is stable. This bit needs 6
cycles of external 3-25 MHz oscillator clock to fall down after HSEON reset.
0: external 3-25 MHz oscillator not ready
1: external 3-25 MHz oscillator ready
Bit 16 HSEON: External high-speed clock enable
Set and cleared by software.
Cleared by hardware to stop the external 3-25MHz oscillator when entering Stop or Standby
mode. This bit can not be reset if the external 3-25 MHz oscillator is used directly or
indirectly as system clock or is selected to become the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
These bits are initialized automatically at startup.
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