Table of Contents
xx Élan™SC520 Microcontroller User’s Manual
Figure 19-1 Watchdog Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2
Figure 20-1 Real-Time Clock Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2
Figure 20-2 RTC Voltage Monitor Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
Figure 20-3 Circuit with Backup Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4
Figure 20-4 Circuit without Backup Battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5
Figure 21-1 UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
Figure 21-2 UART Frame Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
Figure 21-3 UART Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
Figure 22-1 SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-2
Figure 22-2 SSI Four-Pin Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4
Figure 22-3 SSI Simultaneous Transmit and Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4
Figure 22-4 SSI Three-Pin Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-4
Figure 22-5 SSI Typical Half-Duplex Communication, Non-Inverted Phase and Clock Modes . . 22-4
Figure 22-6 SSI Clock Phase and Clock Idle State: Effects on Data . . . . . . . . . . . . . . . . . . . . . . 22-6
Figure 22-7 SSI 4-Bit Read Cycle: Full-Duplex, Non-Inverted Phase, Non-Inverted Clock . . . . . 22-6
Figure 22-8 SSI Back-to-Back Transactions for Full-duplex,
Microwire-Compatible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
Figure 22-9 SSI Timing: TC_INT and BSY_STA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
Figure 23-1 PIO Signal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
Figure 24-1 System Test Mode Timing During a SDRAM Write Cycle (Page Hit) . . . . . . . . . . . . 24-5
Figure 24-2 System Test Mode Timing During an SDRAM Read Cycle (Page Miss). . . . . . . . . . 24-5
Figure 24-3 Write Buffer Test Mode Timing During an SDRAM Write Cycle (Page Hit) . . . . . . . . 24-8
Figure 24-4 Write Buffer Test Mode Timing During a SDRAM Read Cycle (Page Miss) . . . . . . . 24-9
Figure 25-1 Logical Structure of Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
Figure 25-2 Serial Debug Port Data Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
Figure 25-3 Device Identification Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
Figure 25-4 Test Access Port Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
Figure 25-5 Test Logic Operation: Data Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19
Figure 25-6 Test Logic Operation: Instruction Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
Figure 26-1 AMDebug Technology Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
Figure 26-2 12-Pin Connector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3
Figure 26-3 20-Pin Serial Connector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4
Figure 26-4 Mechanical Specifications for AMDebug™ Technology Target Connector . . . . . . . . 26-4
Figure 26-5 Locating the Target Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
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