Table of Contents
Élan™SC520 Microcontroller User’s Manual xix
Figure 10-5 SDRAM Clock Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Figure 10-6 Alternate SDRAM Clock Generation with External Clock Driver . . . . . . . . . . . . . . . . 10-7
Figure 10-7 SDRAM Burst Read Cycle (Read-Ahead Feature Disabled) (Page Miss/Page Hit) . 10-22
Figure 10-8 SDRAM Write Cycle (Write Buffer and ECC Disabled) (Page Miss/page Hit). . . . . . 10-23
Figure 10-9 SDRAM CPU Burst Write (Write Buffer and ECC Disabled) (Page Miss/Page Hit) . 10-24
Figure 10-10 SDRAM Burst Read Cycle with ECC Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
Figure 10-11 SDRAM Read-Modify-Write Cycle (for Data Write) with ECC Enabled (Page Hit) . . 10-26
Figure 10-12 SDRAM Auto Refresh Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
Figure 10-13 SDRAM Mode Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27
Figure 11-1 Write Buffer and Read Buffer Block Diagram (SDRAM Subsystem). . . . . . . . . . . . . 11-2
Figure 11-2 Write Buffer and Read Buffer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Figure 11-3 Write Buffer Merging Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
Figure 11-4 Write Buffer Collapsing Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Figure 11-5 Write Buffer Read-Merging Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
Figure 11-6 Bus Thrashing with Write Buffer Disabled and Enabled . . . . . . . . . . . . . . . . . . . . . 11-14
Figure 12-1 ROM Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Figure 12-2 Voltage Isolation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Figure 12-3 Page-Mode ROM: Fetching Four Words from a 16-Bit ROM . . . . . . . . . . . . . . . . . . 12-6
Figure 12-4 Non-Page-Mode ROM: Fetching Four Words from a 16-Bit ROM . . . . . . . . . . . . . . 12-8
Figure 12-5 Page-Mode ROM: Fetching Four Doublewords (Aligned) from a 32-Bit ROM . . . . . 12-8
Figure 12-6 Page-Mode ROM: Fetching Four Doublewords (Unaligned) from an 8-Bit ROM . . . 12-8
Figure 12-7 Multiple Accesses: Data Amounts Smaller than One Doubleword (2 Bytes)
from an 8-Bit ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Figure 12-8 Page Access for Fetching Four Doublewords from a 32-Bit ROM
(Burst Sequence: 2-1-1-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
Figure 12-9 Page Access for Fetching Two Doublewords from a 16-Bit ROM. . . . . . . . . . . . . . 12-11
Figure 12-10 Cache-Line Fill (Fetching Four Doublewords from a 32-Bit ROM) . . . . . . . . . . . . . 12-11
Figure 12-11 Word Write Cycle to Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
Figure 13-1 GP Bus Controller System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
Figure 13-2 Example: Using an External Data Buffer to Address Excess Loading. . . . . . . . . . . . 13-4
Figure 13-3 Example: Using a Voltage Translator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Figure 13-4 GP Bus Timing Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Figure 13-5 ÉlanSC520 Microcontroller Interfacing with a Super I/O Controller. . . . . . . . . . . . . 13-13
Figure 13-6 Timing Diagram of a Super I/O Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
Figure 13-7 ÉlanSC520 Microcontroller Interfacing with an Am85C30. . . . . . . . . . . . . . . . . . . . 13-15
Figure 13-8 Timing Diagram of an Am85C30 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Figure 13-9 8-Bit Data Access of an 8-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
Figure 13-10 16-Bit Data Access of a 16-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
Figure 13-11 16-Bit Data Access of an 8-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
Figure 13-12 32-Bit Data Access of an 8-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
Figure 13-13 32-Bit Data Access of a 16-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
Figure 13-14 8-Bit Data Access of a 16-Bit I/O Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
Figure 13-15 16-Bit Access of a 16-Bit I/O Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20
Figure 13-16 GPRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-21
Figure 14-1 GP-DMA Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Figure 14-2 Master and Slave Core Cascading Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Figure 14-3 GP-DMA Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13
Figure 14-4 GP-DMA Write Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Figure 14-5 GP-DMA Verify Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14
Figure 14-6 GP-DMA Read in Demand Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16
Figure 14-7 GP-DMA Read Transfer with Cache Hit (Write-Back Cache) . . . . . . . . . . . . . . . . . 14-17
Figure 15-1 Programmable Interrupt Controller (PIC) Block Diagram . . . . . . . . . . . . . . . . . . . . . 15-3
Figure 15-2 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Figure 15-3 Interrupt Source Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
Figure 15-4 NMI Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Figure 16-1 Programmable Interval Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2
Figure 17-1 General-Purpose Timers Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
Figure 18-1 Software Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
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