RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 12 1023/1096
Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR)
Address offset: 0x0168
Reset value: 0x0000 0000
This register contains the number of good frames transmitted.
Ethernet MMC received frames with CRC error counter register
(ETH_MMCRFCECR)
Address offset: 0x0194
Reset value: 0x0000 0000
This register contains the number of frames received with CRC error.
Ethernet MMC received frames with alignment error counter register
(ETH_MMCRFAECR)
Address offset: 0x0198
Reset value: 0x0000 0000
This register contains the number of frames received with alignment (dribble) error.
313029282726252423222120191817161514131211109876543210
TGFC
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Bits 31:0 TGFC: Transmitted good frames counter
313029282726252423222120191817161514131211109876543210
RFCEC
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Bits 31:0 RFCEC: Received frames CRC error counter
Received frames with CRC error counter
313029282726252423222120191817161514131211109876543210
RFAEC
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Bits 31:0 RFAEC: Received frames alignment error counter
Received frames with alignment error counter
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