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Ethernet (ETH): media access control (MAC) with DMA controller RM0008

1022/1096 Doc ID 13902 Rev 12

Ethernet MMC transmitted good frames after a single collision counter

Address offset: 0x014C

Reset value: 0x0000 0000

This register contains the number of successfully transmitted frames after a single collision

in Half-duplex mode.

Ethernet MMC transmitted good frames after more than a single collision

counter register (ETH_MMCTGFMSCCR)

Address offset: 0x0150

Reset value: 0x0000 0000

This register contains the number of successfully transmitted frames after more than a

single collision in Half-duplex mode.

Bit 15 TGFMSCM: Transmitted good frames more single collision mask

Setting this bit masks the interrupt when the transmitted good frames after more than a single

collision counter reaches half the maximum value.

Bit 14 TGFSCM: Transmitted good frames single collision mask

Setting this bit masks the interrupt when the transmitted good frames after a single collision

counter reaches half the maximum value.

Bits 13:0 Reserved

313029282726252423222120191817161514131211109876543210

TGFSCC

rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr

Bits 31:0 TGFSCC: Transmitted good frames single collision counter

Transmitted good frames after a single collision counter.

313029282726252423222120191817161514131211109876543210

TGFMSCC

rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr

Bits 31:0 TGFMSCC: Transmitted good frames more single collision counter

Transmitted good frames after more than a single collision counter

ST STM32F101xx User Manual

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